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DP83902AVF Datasheet(PDF) 6 Page - National Semiconductor (TI) |
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DP83902AVF Datasheet(HTML) 6 Page - National Semiconductor (TI) |
6 / 70 page 20 Pin Description (Continued) PQFP PLCC AVJG Pin IO Description Pin No Pin No Pin No Name BUS INTERFACE PINS (Continued) 43 45 40 BACK I BUS ACKNOWLEDGE Bus Acknowledge is an active high signal indicating that the CPU has granted the bus to the DP83902A If immediate bus access is desired BREQ should be tied to BACK Tying BACK to VCC will result in a deadlock 45 46 42 BREQ O BUS REQUEST Bus Request is an active high signal used to request the bus for DMA transfers This signal is automatically generated when the FIFO needs servicing 52 53 50 RESET I RESET Reset is active low and places the DP83902A in a reset mode immediately No packets are transmitted or received by the DP83902A until STA bit is set Affects Command Register Interrupt Mask Register Data Configuration Register and Transmit Configuration Register The DP83902A will execute reset within 10 BSCK cycles NETWORK INTERFACE PINS 47 48 45 POL O POLARITY A TTLMOS active high output This signal is normally in the low state When the TPI module detects seven consecutive link pulses or three consecutive received packets with reversed polarity POL is asserted 49 50 47 TXETX O TRANSMIT ENABLETRANSMIT A TTLMOS active high output It is asserted for approximately 50 ms whenever the DP83902A transmits data in either AUI or TPI modes 50 51 48 COL O COLLISION A TTLMOS active high output It is asserted for approximately 50 ms whenever the DP83902A detects a collision in either the AUI or TPI modes 51 52 49 TEST I FACTORY TEST INPUT Used to check the chip’s internal functions This should be tied low during normal operation 55 56 54 55 54 55 TXOdb O TWISTED PAIR TRANSMIT OUTPUTS These high drive CMOS level outputs 58 59 56 57 56 57 TXOa are resistively combined external to the chip to produce a differential output TXOb signal with equalization to compensate for Intersymbol Interference (ISI) on the TXOda twisted pair medium 64 65 61 62 61 62 RXIa I TWISTED PAIR RECEIVE INPUTS These inputs feed a differential amplifier RXIb which passes valid data to the ENDEC module 69 67 65 GDLNK IO GOOD LINKLINK DISABLE This pin has a dual function both input and output LNKDIS The function is latched by the DP83902A on the rising edge of the Reset signal ie on the chip returning to normal operation after reset As an output this pin is configured as an open drain N-channel device and is suitable for driving a LED It will be latched as output on removal of chip reset if connected to a LED or left open circuit Under normal conditions (the twisted pair link is not broken) the output will be low and the LED will be lit The open drain output will be switched off if the twisted pair link has been detected to be broken It is recommended that the color of the LED be green This output will be pulled high in AUI mode by an internal resistor of approximately 15 kX When this pin which has an internal pull-up resistor to VDD is tied low it becomes an input and the link integrity checking is disabled 73 70 SQSEL I TPI SQUELCH SELECT This pin selects the TPI module input squelch thresholds When tied low the input squelch threshold on the RXIg inputs complies to 10BASE-T specification When set high the RXIg input operates with reduced squelch levels allowing its use with longer lengths of cable or cable with higher losses If this pin is left unconnected an internal pulldown causes the ST-NIC’s TPI to default to the higher squelch level 70 68 66 20 MHz O 20 MHz This is a TTLMOS level signal It is a buffered version of the oscillator X2 It is suitable to drive external logic 71 69 67 X1 I EXTERNAL OSCILLATOR INPUT 72 70 69 GND I GROUNDX2 If an oscillator is used this pin should be tied to ground and if a X2 crystal is used this pin should be tied directly to the crystal 74 71 71 SEL I MODE SELECT When high TXa and TXb are the same voltage in the idle state When low Transmita is positive with respect to Transmitb in the idle state at the transformer’s primary 6 |
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