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DS92LX1621 Datasheet(PDF) 1 Page - Texas Instruments |
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DS92LX1621 Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 49 page  DS92LX1621, DS92LX1622 www.ti.com SNLS327I – MAY 2010 – REVISED JANUARY 2014 DS92LX1621/DS92LX1622 10 - 50 MHz DC-Balanced Channel Link III Serializer and Deserializer with Bi-Directional Control Channel Check for Samples: DS92LX1621, DS92LX1622 1 FEATURES • SER Package: 32 Pin WQFN (5mm x 5mm) • DES Package: 40 Pin WQFN (6mm x 6mm) 2 • Configurable Data Throughput – 12–bit (min) up to 600 Mbits/sec APPLICATIONS – 16–bit (def) up to 800 Mbits/sec • Industrial Displays, Touch Screens – 18–bit (max) up to 900 Mbits/sec • Medical Imaging • 10 MHz to 50 MHz Input Clock Support • Embedded Clock with DC Balanced Coding to DESCRIPTION Support AC-Coupled Interconnects The DS92LX1621 / DS92LX1622 chipset offers a • Capable to Drive up to 10 Meters Shielded Channel Link III interface with a high-speed forward Twisted-Pair channel and a full-duplex back channel for data transmission over a single differential pair. The • Bi-Directional Control Interface Channel with Serializer/Deserializer pair is targeted for direct I2C Support connections between automotive camera systems • I2C Interface for Device Configuration. Single- and Host Controller/Electronic Control Unit (ECU). pin ID Addressing The primary transport sends 16 bits of image data • 16–bit Data Payload with CRC (Cyclic over a single high-speed serial stream together with a low latency bi-directional control channel transport Redundancy Check) for Checking Data that supports I2C. Included with the 16-bit payload is Integrity with Programmable Data a selectable data integrity option for CRC (Cyclic Transmission Error Detection and Interrupt Redundancy Check) or parity bit to monitor Control transmission link errors. Using TI’s embedded clock • Up to 6 Programmable GPIO's technology allows transparent full-duplex • AT-SPEED BIST Diagnosis Feature to Validate communication over a single differential pair, carrying asymmetrical bi-directional control information without Link Integrity the dependency of video blanking intervals. This • Individual Power-Down Controls for Both SER single serial stream simplifies transferring a wide data and DES bus over PCB traces and cable by eliminating the • User-Selectable Clock Edge for Parallel Data skew problems between parallel data and clock on Both SER and DES paths. This significantly saves system cost by narrowing data paths that in turn reduce PCB layers, • Integrated Termination Resistors cable width, and connector size and pins. • 1.8V- or 3.3V-Compatible Parallel Bus Interface In addition, the Deserializer inputs provide • Single Power Supply at 1.8V equalization control to compensate for loss from the • IEC 61000–4–2 ESD Compliant media over longer distances. Internal DC balanced • No Reference Clock Required on Deserializer encoding/decoding is used to support AC-Coupled interconnects. • Programmable Receive Equalization • LOCK Output Reporting Pin to Ensure Link The sleep function provides a power-savings mode Status and a remote wake up interrupt for signaling of a remote device. • EMI/EMC Mitigation The Serializer is offered in a 32-pin WQFN package, – DES Programmable Spread Spectrum and Deserializer is offered in a 40-pin WQFN (SSCG) Outputs package. – DES Receiver Staggered Outputs • Temperature Range −40°C to +85°C 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2010–2014, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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