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DS92LV1224TMSA Datasheet(PDF) 4 Page - Texas Instruments |
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DS92LV1224TMSA Datasheet(HTML) 4 Page - Texas Instruments |
4 / 23 page DS92LV1224 SNLS189A – APRIL 2005 – REVISED APRIL 2013 www.ti.com Powerdown When no data transfer occurs, you can use the Powerdown state. The Serializer and Deserializer use the Powerdown state, a low power sleep mode, to reduce power consumption. The Deserializer enters Powerdown when you drive PWRDN and REN low. The Serializer enters Powerdown when you drive PWRDN low. In Powerdown, the PLL stops and the outputs enter TRI-STATE, which disables load current and reduces supply current to the milliampere range. To exit Powerdown, you must drive the PWRDN pin high. Before valid data exchanges between the Serializer and Deserializer, you must reinitialize and resynchronize the devices to each other. Initialization of the Serializer takes 510 TCLK cycles. The Deserializer will initialize and assert LOCK high until lock to the Bus LVDS clock occurs. TRI-STATE The Serializer enters TRI-STATE when the DEN pin is driven low. This puts both driver output pins (DO+ and DO −) into TRI-STATE. When you drive DEN high, the Serializer returns to the previous state, as long as all other control pins remain static (SYNC1, SYNC2, PWRDN, TCLK_R/F). When you drive the REN pin low, the Deserializer enters TRI-STATE. Consequently, the receiver output pins (ROUT0–ROUT9) and RCLK will enter TRI-STATE. The LOCK output remains active, reflecting the state of the PLL. Table 1. (1) Random Lock Times for the DS92LV1224 40 MHz 66 MHz Units Maximum 26 18 μs Mean 4.5 3.0 μs Minimum 0.77 0.43 μs Conditions: PRBS 215, VCC = 3.3V (1) Difference in lock times are due to different starting points in the data pattern with multiple parts. 4 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: DS92LV1224 |
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