DS92LV1212

16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer

with Embedded Clock Recovery

General Description

The DS92LV1212 is an upgrade of the DS92LV1210. It

maintains all of the features of the DS92LV1210 with the ad-

ditional capability of locking to the incoming data stream

without the need of SYNC patterns. This makes the

DS92LV1212 useful in applications where the Deserializer

must be operated “open-loop” — without a feedback path

from the Deserializer to the Serializer. The DS92LV1212 is

designed to be used with the DS92LV1021 Bus LVDS Serial-

izer. The DS92LV1212 receives a Bus LVDS serial data

stream and transforms it into a 10-bit wide parallel data bus

and separate clock. The reduced cable, PCB trace count

and connector size saves cost and makes PCB layout

easier. Clock-to-data and data-to-data skews are eliminated

since one input receives both clock and data bits serially.

The powerdown pin is used to save power by reducing the

supply current when the device is not in use. The Deserial-

izer will establish lock to a synchronization pattern within

specified lock times but it can also lock to a data stream with-

out SYNC patterns.

Features

n Clock recovery without SYNC patterns-random lock

n Guaranteed transition every data transfer cycle

40MHz

n Single differential pair eliminates multi-channel skew

n 400 Mbps serial Bus LVDS bandwidth (at 40 MHz clock)

n 10-bit parallel interface for 1 byte data plus 2 control bits

or UTOPIA I Interface

n Synchronization mode and LOCK indicator

n Flow-through pinout for easy PCB layout

n High impedance on receiver inputs when power is off

n Programmable edge trigger on clock

n Footprint compatible with DS92LV1210

n Small 28-lead SSOP package-MSA

Block Diagram

DS100982-1

April 1999

© 1999 National Semiconductor Corporation

DS100982

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