NRND

DS92LV1023

www.ti.com

SNLS049D – MAY 2000 – REVISED APRIL 2013

Figure 13. Random Lock Hot Insertion

Pin Diagram

Figure 14. DS92LV1023TMSA - Serializer

SSOP Package

See Package Number DB0028A

SERIALIZER PIN DESCRIPTIONS

Pin Name

No.

I/O

Description

DIN

3–12

I

Data Input. LVTTL levels inputs. Data on these pins are loaded into a 10-bit input register.

TCLK_R/F

13

I

Transmit Clock Rising/Falling strobe select. LVTTL level input. Selects TCLK active edge for

strobing of DIN data. High selects rising edge. Low selects falling edge.

DO+

22

O

+ Serial Data Output. Non-inverting Bus LVDS differential output.

DO

−

21

O

− Serial Data Output. Inverting Bus LVDS differential output.

DEN

19

I

Serial Data Output Enable. LVTTL level input. A low, puts the Bus LVDS outputs in TRI-STATE.

PWRDN

24

I

Powerdown. LVTTL level input. PWRDN driven low shuts down the PLL and TRI-STATEs outputs

putting the device into a low power sleep mode.

TCLK

14

I

Transmit Clock. LVTTL level input. Input for 40 MHz–66 MHz (nominal) system clock.

SYNC

1, 2

I

Assertion of SYNC (high) for at least 1024 synchronization symbols to be transmitted on the Bus

LVDS serial output. Synchronization symbols continue to be sent if SYNC continues asserted. TTL

level input. The two SYNC pins are ORed.

DVCC

27, 28

I

Digital Circuit power supply.

DGND

15, 16

I

Digital Circuit ground.

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