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DS91C180 Datasheet(PDF) 5 Page - Texas Instruments

Part No. DS91C180
Description  100 MHz M-LVDS Line Driver/Receiver Pair
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Maker  TI1 [Texas Instruments]
Homepage  http://www.ti.com
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DS91C180 Datasheet(HTML) 5 Page - Texas Instruments

 
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DS91C180, DS91D180
www.ti.com
SNLS158M – MARCH 2006 – REVISED APRIL 2013
Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
(1)(2)(3)(4)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CA/B,
Receiver input or driver output capacitance balance
1.0
CY/Z
(CA/CB or CY/CZ)
SUPPLY CURRENT (VCC)
ICCD
Driver Supply Current
RL = 50Ω, DE = VCC, RE = VCC
17
29.5
mA
ICCZ
TRI-STATE Supply Current
DE = GND, RE = VCC
7
9.0
mA
ICCR
Receiver Supply Current
DE = GND, RE = GND
14
18.5
mA
ICCB
Supply Current, Driver and Receiver Enabled
DE = VCC, RE = GND
20
29.5
mA
Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
(1) (2)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DRIVER AC SPECIFICATION
tPLH
Differential Propagation Delay Low to High
RL = 50Ω, CL = 5 pF,
1.0
3.4
5.5
ns
tPHL
Differential Propagation Delay High to Low
CD = 0.5 pF
1.0
3.1
5.5
ns
tSKD1 (tsk(p))
Pulse Skew |tPLHD − tPHLD|
(3) (4)
Figure 8 and Figure 9
300
420
ps
tSKD3
Part-to-Part Skew (5) (4)
1.9
ns
tTLH (tr)
Rise Time (4)
1.0
1.8
3.0
ns
tTHL (tf)
Fall Time (4)
1.0
1.8
3.0
ns
tPZH
Enable Time (Z to Active High)
RL = 50Ω, CL = 5 pF,
8
ns
tPZL
Enable Time (Z to Active Low )
CD = 0.5 pF
8
ns
tPLZ
Disable Time (Active Low to Z)
Figure 10 and Figure 11
8
ns
tPHZ
Disable Time (Active High to Z)
8
ns
tJIT
Random Jitter, RJ (4)
100MHz clock pattern(6)
2.5
5.5
psrms
fMAX
Maximum Data Rate
200
Mbps
RECEIVER AC SPECIFICATION
tPLH
Propagation Delay Low to High
CL = 15 pF
2.0
4.7
7.5
ns
tPHL
Propagation Delay High to Low
Figure 12 Figure 13 and Figure 14
2.0
5.3
7.5
ns
tSKD1 (tsk(p))
Pulse Skew |tPLHD − tPHLD|
(3) (4)
0.6
1.9
ns
tSKD3
Part-to-Part Skew (5)(4)
1.5
ns
tTLH (tr)
Rise Time(4)
0.5
1.2
3.0
ns
tTHL (tf)
Fall Time(4)
0.5
1.2
3.0
ns
tPZH
Enable Time (Z to Active High)
RL = 500Ω, CL = 15 pF
10
ns
tPZL
Enable Time (Z to Active Low)
Figure 15 and Figure 16
10
ns
tPLZ
Disable Time (Active Low to Z)
10
ns
tPHZ
Disable Time (Active High to Z)
10
ns
fMAX
Maximum Data Rate
200
Mbps
(1)
All typicals are given for V = 3.3V and TA = 25°C.
(2)
CL includes fixture capacitance and CD includes probe capacitance.
(3)
tSKD1, |tPLHD − tPHLD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative
going edge of the same channel.
(4)
Not production tested. Ensured by a statistical analysis on a sample basis at the time of characterization.
(5)
tSKD3, Part-to-Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This
specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
(6)
Stimulus and fixture jitter has been subtracted.
Copyright © 2006–2013, Texas Instruments Incorporated
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Product Folder Links: DS91C180 DS91D180


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