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DS91C180 Datasheet(PDF) 3 Page - Texas Instruments

Part No. DS91C180
Description  100 MHz M-LVDS Line Driver/Receiver Pair
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Maker  TI1 [Texas Instruments]
Homepage  http://www.ti.com
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DS91C180 Datasheet(HTML) 3 Page - Texas Instruments

 
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DS91C180, DS91D180
www.ti.com
SNLS158M – MARCH 2006 – REVISED APRIL 2013
Absolute Maximum Ratings
(1) (2)
Supply Voltage, VCC
−0.3V to +4V
Control Input Voltages
−0.3V to (VCC + 0.3V)
Driver Input Voltage
−0.3V to (VCC + 0.3V)
Driver Output Voltages
−1.8V to +4.1V
Receiver Input Voltages
−1.8V to +4.1V
Receiver Output Voltage
−0.3V to (VCC + 0.3V)
Maximum Package Power Dissipation at +25°C
SOIC Package
1.1 W
Derate SOIC Package
8.8 mW/°C above +25°C
Thermal Resistance (4-Layer, 2 oz. Cu, JEDEC)
θJA
113.7 °C/W
θJC
36.9 °C/W
Maximum Junction Temperature
150°C
Storage Temperature Range
−65°C to +150°C
Lead Temperature (Soldering, 4 seconds)
260°C
ESD Ratings:
(HBM 1.5k
Ω, 100pF)
≥ 5 kV
(EIAJ 0
Ω, 200pF)
≥ 250 V
(CDM 0
Ω, 0pF)
≥ 1000 V
(1)
“Absolute Maximum Ratings” are those beyond which the safety of the device cannot be ensured. They are not meant to imply that the
device should be operated at these limits. The tables of “Electrical Characteristics” provide conditions for actual device operation.
(2)
If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
Recommended Operating Conditions
Min
Typ
Max
Units
Supply Voltage, VCC
3.0
3.3
3.6
V
Voltage at Any Bus Terminal (Separate or Common-Mode)
−1.4
+3.8
V
Differential Input Voltage VID
2.4
V
High Level Input Voltage VIH
2.0
VCC
V
Low Level Input Voltage VIL
0
0.8
V
Operating Free Air Temperature TA
−40
+25
+85
°C
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
(1) (2) (3) (4)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
M-LVDS Driver
|VYZ|
Differential output voltage magnitude
RL = 50Ω, CL = 5pF
480
650
mV
Figure 3 and Figure 5
ΔVYZ
Change in differential output voltage magnitude
−50
0
+50
mV
between logic states
VOS(SS)
Steady-state common-mode output voltage
RL = 50Ω, CL = 5pF
0.3
1.8
2.1
V
Figure 3 and Figure 4
|
ΔVOS(SS)|
Change in steady-state common-mode output voltage
0
+50
mV
between logic states
VOS(PP)
Peak-to-peak common-mode output voltage
(VOS(pp) @ 500KHz clock)
143
mV
VY(OC)
Maximum steady-state open-circuit output voltage
Figure 6
0
2.4
V
VZ(OC)
Maximum steady-state open-circuit output voltage
0
2.4
V
VP(H)
Voltage overshoot, low-to-high level output
RL = 50Ω, CL = 5pF,
1.2VSS
V
CD = 0.5pF
VP(L)
Voltage overshoot, high-to-low level output
−0.2VSS
V
Figure 8 and Figure 9(5)
IIH
High-level input current (LVTTL inputs)
VIH = 2.0V
-15
15
μA
(1)
All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless
otherwise specified.
(2)
All typicals are given for VCC = 3.3V and TA = 25°C.
(3)
The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this datasheet.
(4)
CL includes fixture capacitance and CD includes probe capacitance.
(5)
Not production tested. Ensured by a statistical analysis on a sample basis at the time of characterization.
Copyright © 2006–2013, Texas Instruments Incorporated
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Product Folder Links: DS91C180 DS91D180


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