REV. G

ADM3307E/ADM3310E/ADM3311E/ADM3312E/ADM3315E

–13–

RECEIVER

OUTPUT

EN INPUT

0V

3V

Figure 5. Receiver Disable Timing

RECEIVER

OUTPUT

EN INPUT

3V

0.4V

0V

3V

Figure 6. Receiver Enable Timing

High Baud Rate

The ADM33xxE features high slew rates, permitting data trans-

mission at rates well in excess of the EIA/RS-232E specifications.

RS-232 voltage levels are maintained at data rates up to 230 kbps

(460 kbps for ADM3307E) under worst-case loading conditions.

This allows for high speed data links between two terminals.

LAYOUT AND SUPPLY DECOUPLING

Because of the high frequencies at which the ADM33xxE oscillator

operates, particular care should be taken with printed circuit

board layout, with all traces being as short as possible and C1 to

C3 being connected as close to the device as possible. The use

of a ground plane under and around the device is also highly

recommended.

When the oscillator starts up during Green Idle operation, large

decoupled with a parallel combination of 10

mF tantalum and

0.1

possible.

Capacitors C1 to C3 can have values between 0.1

mF and 1 mF.

Larger values give lower ripple. These capacitors can be either

electrolytic capacitors chosen for low equivalent series resistance

(ESR) or nonpolarized types, but the use of ceramic types is

highly recommended. If polarized electrolytic capacitors are

used, polarity must be observed (as shown by C1+).

ESD/EFT TRANSIENT PROTECTION SCHEME

The ADM33xxE uses protective clamping structures on all inputs

and outputs that clamp the voltage to a safe level and dissipate

the energy present in ESD (electrostatic) and EFT (electrical fast

transients) discharges. A simplified schematic of the protection

structure is shown below in Figures 7a and 7b (see Figures 8a and

8b for ADM3307E protection structure). Each input and output

contains two back-to-back high speed clamping diodes. During nor-

mal operation with maximum RS-232 signal levels, the diodes have

no effect as one or the other is reverse biased depending on the

polarity of the signal. If however the voltage exceeds about

±50 V,

reverse breakdown occurs and the voltage is clamped at this level.

The diodes are large p-n junctions designed to handle the

instantaneous current surge that can exceed several amperes.

The transmitter outputs and receiver inputs have a similar protec-

tion structure. The receiver inputs can also dissipate some of the

energy through the internal 5 k

W (or 22 kW for the ADM3310E)

resistor to GND as well as through the protection diodes.

Rx

D1

D2

RECEIVER

INPUT

Figure 7a. Receiver Input Protection Scheme

Tx

D1

D2

TRANSMITTER

OUTPUT

Figure 7b. Transmitter Output Protection Scheme

The ADM3307E protection scheme is slightly different (see

Figures 8a and 8b). The receiver inputs, transmitter inputs, and

transmitter outputs contain two back-to-back high speed clamping

diodes. The receiver outputs (CMOS outputs), SD and

EN pins

contain a single reverse biased high speed clamping diode. Under

normal operation with maximum CMOS signal levels, the receiver

output, SD, and

EN protection diodes have no effect because

they are reversed biased. If, however, the voltage exceeds about

15 V, reverse breakdown occurs and the voltage is clamped at

this level. If the voltage reaches –0.7 V, the diode is forward

biased and the voltage is clamped at this level. The receiver inputs

can also dissipate some of the energy through the internal 5 k

W

resistor to GND as well as through the protection diodes.

D3

D1

D2

RECEIVER

INPUT

RECEIVER

OUTPUT

Rx

Figure 8a. ADM3307E Receiver Input Protection Scheme

Tx

D1

D2

TRANSMITTER

INPUT

TRANSMITTER

OUTPUT

D3

D4

Figure 8b. ADM3307E Transmitter Output Protection Scheme

The protection structures achieve ESD protection up to

±15 kV on

all RS-232 I/O lines (and all CMOS lines, including SD and

EN

for the ADM3307E). The methods used to test the protection

scheme are discussed later.