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DS90UH947TRGCRQ1 Datasheet(PDF) 4 Page - Texas Instruments |
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DS90UH947TRGCRQ1 Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 87 page  DS90UH947-Q1 SNLS455 – NOVEMBER 2014 www.ti.com Pin Functions (continued) Pin Name Pin # I/O, Type Description LFOLDI 63 Analog OpenLDI Loop Filter Connect to a 10nF capacitor to GND FPD-Link III Serial Pins DOUT0- 26 I/O FPD-Link III Inverting Output 0 The output must be coupled with a 33nF capacitor DOUT0+ 27 I/O FPD-Link III True Output 0 The output must be coupled with a 33nF capacitor DOUT1- 22 I/O FPD-Link III Inverting Output 1 The output must be coupled with a 33nF capacitor DOUT1+ 23 I/O FPD-Link III True Output 1 The output must be coupled with a 33nF capacitor LF 20 Analog FPD-Link III Loop Filter Connect to a 10nF capacitor to GND Control Pins SDA 48 IO, Open-Drain I2C Data Input / Output Interface Open drain. Must have an external pull-up resistor to 1.8V or 3.3V. DO NOT FLOAT. Recommended pull-up: 4.7k Ω. SCL 47 IO, Open-Drain I2C Clock Input / Output Interface Open drain. Must have an external pull-up resistor to 1.8V or 3.3V. DO NOT FLOAT. Recommended pull-up: 4.7k Ω. I2CSEL 13 I, LVCMOS I2C Voltage Level Strap Option Tie to VDDIO with a 10kΩ resistor for 1.8V I2C operation. Leave floating for 3.3V I2C operation. This pin is read as an input at power up. IDx 19 I, Analog I2C Address Select External pull-up to VDD18 is required under all conditions. DO NOT FLOAT. Connect to external pull-up and pull-down resistors to create a voltage divider. MODE_SEL0 18 Analog Mode Select 0 Input. Refer to Table 7. MODE_SEL1 32 Analog Mode Select 1 Input. Refer to Table 8. PDB 31 I, LVCMOS Power-Down Mode Input Pin INTB 49 O, Open-Drain Remote interrupt INTB = H, Normal Operation INTB = L, Interrupt Request Recommended pull-up: 4.7k Ω to VDDIO. DO NOT FLOAT. REM_INTB 10 O, LVCMOS LVCMOS Output REM_INTB will directly mirror the status of the INTB_IN signal from the remote device. No separate serializer register read will be required to reset and change the status of this pin. SPI Pins MOSI 46 IO, LVCMOS SPI Master Output Slave Input Only available in Dual Link Mode. Shared with D_GPIO0 MISO 45 IO, LVCMOS SPI Master Input Slave Output Only available in Dual Link Mode. Shared with D_GPIO1 SPLK 44 IO, LVCMOS SPI Clock Only available in Dual Link Mode. Shared with D_GPIO2 SS 43 IO, LVCMOS SPI Slave Select Only available in Dual Link Mode. Shared with D_GPIO3 High Speed GPIO Pins D_GPIO0 46 IO, LVCMOS High Speed GPIO0 Only available in Dual Link Mode. Shared with MOSI D_GPIO1 45 IO, LVCMOS High Speed GPIO1 Only available in Dual Link Mode. Shared with MISO D_GPIO2 44 IO, LVCMOS High Speed GPIO2 Only available in Dual Link Mode. Shared with SPLK D_GPIO3 43 IO, LVCMOS High Speed GPIO3 Only available in Dual Link Mode. Shared with SS GPIO Pins 4 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH947-Q1 |
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