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DS90UH928Q-Q1 Datasheet(PDF) 7 Page - Texas Instruments |
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DS90UH928Q-Q1 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 69 page  7 DS90UH928Q-Q1 www.ti.com SNLS440C – MARCH 2013 – REVISED JULY 2016 Product Folder Links: DS90UH928Q-Q1 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) For soldering specifications, see product folder at www.ti.com and SNOA549. (3) The DS90UH928Q-Q1VDD33 and VDDIO voltages require a specific ramp rate during power up. The power supply ramp time must be less than 1.5 ms with a monotonic rise. 7 Specifications 7.1 Absolute Maximum Ratings (1) (2) MIN MAX UNIT Supply Voltage – VDD33 (3) −0.3 4 V Supply Voltage – VDDIO (3) −0.3 4 V LVCMOS I/O Voltage −0.3 (VDDIO + 0.3) V Deserializer Input Voltage −0.3 2.75 V Junction Temperature 150 °C Storage temperature, Tstg −65 150 °C (1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 7.2 ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002, all pins(1) ±8000 V Charged device model (CDM), per AEC Q100-011, all pins ±1250 V Machine model (MM) ±250 V (IEC, powered-up only) RD = 330 Ω, CS = 150 pF Air Discharge (Pins 40, 41, 44, and 45) ±15000 V Contact Discharge (Pins 40, 41, 44, and 45) ±8000 V (ISO10605) RD = 330 Ω, CS = 150 pF Air Discharge (Pins 40, 41, 44, and 45) ±15000 V Contact Discharge (Pins 40, 41, 44, and 45) ±8000 V (ISO10605) RD = 2 kΩ, CS = 150 pF or 330 pF Air Discharge (Pins 40, 41, 44, and 45) ±15000 V Contact Discharge (Pins 40, 41, 44, and 45) ±8000 V (1) The DS90UH928Q-Q1VDD33 and VDDIO voltages require a specific ramp rate during power up. The power supply ramp time must be less than 1.5 ms with a monotonic rise. (2) VDDIO should not exceed VDD33 by more than 300 mV (VDDIO < VDD33 + 0.3 V). (3) Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC-coupled to the VDD33 and VDDIO supplies with amplitude >100 mVp-p measured at the device VDD33 and VDDIO pins. Bit error rate testing of input to the Ser and output of the Des with 10 meter cable shows no error when the noise frequency on the Ser is less than 50 MHz. The Des on the other hand shows no error when the noise frequency is less than 50 MHz. 7.3 Recommended Operating Conditions MIN NOM MAX UNIT Supply Voltage (VDD33) (1) 3 3.3 3.6 V LVCMOS Supply Voltage (VDDIO) (1) (2) Connect VDDIO to 3.3 V and use 3.3 V IOs 3 3.3 3.6 V Connect VDDIO to 1.8 V and use 1.8 V IOs 1.71 1.8 1.89 V Operating Free Air Temperature (TA) −40 25 105 °C PCLK Frequency (out of TxCLKOUT±) 5 85 MHz Supply Noise(3) 100 mVP-P |
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