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DS90UH927Q-Q1 Datasheet(PDF) 9 Page - Texas Instruments |
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DS90UH927Q-Q1 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 68 page  DS90UH927Q-Q1 www.ti.com SNLS433C – NOVEMBER 2012 – REVISED JANUARY 2015 6.6 AC Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) (3) PARAMETER TEST CONDITIONS PIN/FREQ. MIN TYP MAX UNIT FPD-LINK LVDS INPUT tRSP Receiver Strobe Position See Figure 4 RxCLKIN±, 0.25 0.5 0.75 UI RXIN[3:0]± FPD-LINK III CML I/O tLHT CML Output Low-to-High Transition 100 140 ps Time DOUT+, See Figure 3 DOUT- tHLT CML Output High-to-Low Transition 100 140 ps Time tPLD See Figure 5, (4) PCLK = 5 MHz Serializer PLL Lock Time 5 ms to 85 MHz tSD Delay — Latency See Figure 6 146*T ns Checkerboard Pattern 0.17 0.2 UI Output Total Jitter, PCLK=5 MHz, see Figure 8 tTJIT Bit Error Rate ≤1E-9, see Figure 7, (5) RxCLKIN± Checkerboard Pattern (6) (7) (8) (9) 0.26 0.29 UI PCLK=85 MHz, see Figure 8 f/40 < Jitter Freq < f/20, DES = 0.6 UI DS90UH926Q-Q1 Input Jitter Tolerance, Bit Error Rate RxCLKIN±, f = tIJIT ≤1E-9 (8) (10) 78 MHz f/40 < Jitter Freq < f/20, DES = 0.5 UI DS90UH928Q-Q1 I2S RECEIVER TI2S RxCLKIN± f=5 MHz to 85 MHz I2S_CLK, >4 / ns I2S Clock Period, see Figure 10, (7) (11) PCLK = 5 MHz PCLK or to 85 MHz >77 THC I2S_CLK 0.35 TI2S I2S Clock High Time, see Figure 10, (11) TLC I2S_CLK 0.35 TI2S I2S Clock Low Time, see Figure 10, (11) tsr I2S_WC 0.2 TI2S I2S Set-up Time I2S_D[A,B,C,D] thtr I2S_WC 0.2 TI2S I2S Hold Time I2S_D[A,B,C,D] OTHER I/O GPIO[3:0], tGPIO,FC GPIO Pulse Width, Forward Channel PCLK = 5 MHz >2/PCLK s to 85 MHz tGPIO,BC GPIO Pulse Width, Back Channel GPIO[3:0] 20 µs (1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and are not ensured. (2) Typical values represent most likely parametric norms at VDD33 = 3.3V, VDDIO = 1.8V or 3.3V, TA = 25°C, and at the Recommended Operating Conditions at the time of product characterization and are not ensured. (3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD and ΔVOD, which are differential voltages. Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC coupled to the supply pins with amplitude = 100 mVp-p measured at the device VDD33 and VDDIO pins. Bit error rate testing of input to the serializer and output of the deserializer with 10 meter cable shows no error when the noise frequency is less than 50 MHz. (4) tPLD is the time required by the device to obtain lock when exiting power-down state with an active PCLK. (5) Output jitter specs are dependent upon the input clock jitter at the SER. (6) UI – Unit Interval is equivalent to one ideal serialized bit width. The UI scales with PCLK frequency. (7) Specification is ensured by design and is not tested in production. (8) Specification is ensured by characterization and is not tested in production. (9) tTJIT (@BER of 1E-9) specifies the allowable jitter on RxCLKIN±. (10) Jitter Frequency is specified in conjunction with DS90UH928Q-Q1 PLL bandwidth. (11) I2S specifications for tLC and tHC pulses must each be greater than 2 PCLK periods to ensure sampling and supersedes the 0.35*TI2S_CLK requirement. tLC and tHC must be longer than the greater of either 0.35*TI2S_CLK or 2*PCLK. Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: DS90UH927Q-Q1 |
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