DS90UB925Q-Q1 datasheet(21/51 Pages) TI1

Part #	DS90UB925Q-Q1

Description	5 to 85 MHz 24-Bit Color FPD-Link III Serializer With Bidirectional Control Channel

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BIST

start

BIST

stop

BIST

Wait

Step 1: DES in BIST

Step 2: Wait, SER in BIST

Step 3: DES in Normal Mode -

check PASS

Step 4: DES/SER in Normal

Normal

DS90UB925Q-Q1

www.ti.com

SNLS407D – APRIL 2012 – REVISED OCTOBER 2014

Step 1: For the DS90UB925Q-Q1 and DS90UB926Q-Q1 FPD-Link III chipset, BIST Mode is enabled via the

BISTEN pin of DS90UB926Q-Q1 FPD-Link III deserializer. The desired clock source is selected through BISTC

pin.

Step 2: The DS90UB925Q-Q1 serializer is woken up through the back channel if it is not already on. The all zero

pattern on the data pins is sent through the FPD-Link III to the deserializer. Once the serializer and the

deserializer are in BIST mode and the deserializer acquires Lock, the PASS pin of the deserializer goes high and

BIST starts checking the data stream. If an error in the payload (1 to 35) is detected, the PASS pin will switch low

for one half of the clock period. During the BIST test, the PASS output can be monitored and counted to

determine the payload error rate.

Step 3: To Stop the BIST mode, the deserializer BISTEN pin is set Low. The deserializer stops checking the

data. The final test result is held on the PASS pin. If the test ran error free, the PASS output will be High. If there

was one or more errors detected, the PASS output will be Low. The PASS output state is held until a new BIST

is run, the device is RESET, or Powered Down. The BIST duration is user controlled by the duration of the

BISTEN signal.

Step 4: The Link returns to normal operation after the deserializer BISTEN pin is low. Figure 14 shows the

waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple

errors. In most cases it is difficult to generate errors due to the robustness of the link (differential data

transmission etc.), thus they may be introduced by greatly extending the cable length, faulting the interconnect,

reducing signal condition enhancements ( Rx Equalization).

Figure 13. Bist Mode Flow Diagram

7.3.18.2 Forward Channel And Back Channel Error Checking

While in BIST mode, the serializer stops sampling RGB input pins and switches over to an internal all-zero

pattern. The internal all-zeroes pattern goes through scrambler, dc-balancing etc. and goes over the serial link to

the deserializer. The deserializer on locking to the serial stream compares the recovered serial stream with all-

zeroes and records any errors in status registers and dynamically indicates the status on PASS pin. The

deserializer then outputs a SSO pattern on the RGB output pins.

The back-channel data is checked for CRC errors once the serializer locks onto back-channel serial stream as

indicated by link detect status (register bit 0x0C[0]). The CRC errors are recorded in an 8-bit register. The

register is cleared when the serializer enters the BIST mode. As soon as the serializer exits BIST mode, the

functional mode CRC register starts recording the CRC errors. The BIST mode CRC error register is active in

BIST mode only and keeps the record of last BIST run until cleared or enters BIST mode again.

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