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DS90UB924-Q1 Datasheet(PDF) 9 Page - Texas Instruments |
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DS90UB924-Q1 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 62 page  9 DS90UB924-Q1 www.ti.com SNLS512 – APRIL 2016 Product Folder Links: DS90UB924-Q1 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated (1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and are not ensured. (2) Typical values represent most likely parametric norms at VDD33 = 3.3 V, VDDIO = 1.8 V or 3.3 V, TA = 25°C, and at the Recommended Operating Conditions at the time of product characterization and are not ensured. (3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD and ΔVOD, which are differential voltages. (4) Specification is ensured by design and is not tested in production. (5) I2S specifications for tLC and tHC pulses must each be greater than 2 PCLK period to ensure sampling and supersedes the 0.35*TI2S_CLK requirement. tLC and tHC must be longer than the greater of either 0.35*TI2S_CLK or 2*PCLK. 6.6 AC Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) (3) PARAMETER TEST CONDITIONS PIN/FREQ. MIN TYP MAX UNIT GPIO tGPIO,FC GPIO Pulse Width, Forward Channel See (4) GPIO[3:0], PCLK = 5MHz to 96MHz 2/PCLK s tGPIO,BC GPIO Pulse Width, Back Channel See (4) GPIO[3:0] 20 µs RESET tLRST PDB Reset Low Pulse See (4) PDB 2 ms LOOP-THROUGH MONITOR OUTPUT EW Differential Output Eye Opening Width(4) RL = 100 Ω, Jitter freq > f/40 CMLOUTP, CMLOUTN 0.4 UI EH Differential Output Eye Height 300 mV FPD-LINK (OpenLDI) LVDS OUTPUT tTLHT Low -to-High Transition Time RL = 100 Ω TxCLK±, TxOUT[3:0]± 0.25 0.5 ns tTHLT High-to-Low Transition Time 0.25 0.5 ns tDCCJ Cycle-to-Cycle Output Jitter 5 MHz ≤ PCLK ≤ 96 MHz TxCLK± 40 65 ps tTTPn Transmitter Pulse Position 5 MHz ≤ PCLK ≤ 96 MHz n=[6:0] for bits [6:0] See Figure 13 TxOUT[3:0]± 0.5 + n UI ΔtTTP Offset Transmitter Pulse Position (bit 6 - bit 0) PCLK = 96 MHz 0.1 UI tDD Delay Latency 147*T T tTPDD Power Down Delay Active to OFF 900 µs tTXZR Enable Delay OFF to Active 6 ns FPD-LINK III INPUT tDDLT Lock Time (4) 5 MHz ≤ PCLK ≤ 96 MHz RIN±, LOCK 6 40 ms LVCMOS OUTPUTS tCLH Low-to-High Transition Time CL = 8 pF LOCK, PASS 3 7 ns tCHL High-to-Low Transition Time 2 5 ns BIST MODE tPASS BIST PASS Valid Time PASS 800 ns I2S TRANSMITTER tJ Clock Output Jitter MCLK 2 ns TI2S I2S Clock Period Figure 10, (4) (5) PCLK=5 MHz to 96 MHz I2S_CLK, PCLK = 5MHz to 96MHz 4/PCLK or 1/12.288 MHz ns THC_I2S I2S Clock High Time Figure 10, (5) I2S_CLK 0.35 TI2S TLC_I2S I2S Clock Low Time Figure 10, (5) I2S_CLK 0.35 TI2S tSR_I2S I2S Set-up Time Figure 10, I2S_WC I2S_D[A:D] 0.2 TI2S tHR_I2S I2S Hold Time Figure 10 I2S_WC I2S_D[A:D] 0.2 TI2S |
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