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DS90UB903QSQE/NOPB Datasheet(PDF) 4 Page - Texas Instruments |
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DS90UB903QSQE/NOPB Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 47 page  DS90UB903Q, DS90UB904Q SNLS332E – JUNE 2010 – REVISED APRIL 2013 www.ti.com DS90UB903Q SERIALIZER PIN DESCRIPTIONS (continued) Pin Name Pin No. I/O, Type Description Power down Mode Input Pin. PDB = H, Serializer is enabled and is ON. Input, LVCMOS PDB 13 PDB = L, Serailizer is in Power Down mode. When the Serializer is in Power Down, w/ pull down the PLL is shutdown, and IDD is minimized. Programmed control register data are NOT retained and reset to default values Input, LVCMOS Reserved. RES 10, 11 w/ pull down This pin MUST be tied LOW. FPD-LINK III INTERFACE Input/Output, Non-inverting differential output, bidirectional control channel input. The interconnect DOUT+ 17 CML must be AC Coupled with a 100 nF capacitor. DOUT- 16 Input/Output, Inverting differential output, bidirectional control channel input. The interconnect must CML be AC Coupled with a 100 nF capacitor. POWER AND GROUND VDDPLL 14 Power, Analog PLL Power, 1.8V ±5% VDDT 15 Power, Analog Tx Analog Power, 1.8V ±5% VDDCML 18 Power, Analog CML & Bidirectional Channel Driver Power, 1.8V ±5% VDDD 34 Power, Digital Digital Power, 1.8V ±5% Power, Digital Power for I/O stage. The single-ended inputs and SDA, SCL are powered from VDDIO. VDDIO 31 VDDIO can be connected to a 1.8V ±5% or 3.3V ±10% Ground, DAP DAP must be grounded. DAP is the large metal contact at the bottom side, located at VSS DAP the center of the WQFN package. Connected to the ground plane (GND) with at least 16 vias. 4 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: DS90UB903Q DS90UB904Q |
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