DS90UB903Q, DS90UB904Q

SNLS332E – JUNE 2010 – REVISED APRIL 2013

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DS90UB904Q DESERIALIZER PIN DESCRIPTIONS (continued)

Pin Name

Pin No.

I/O, Type

Description

Power down Mode Input Pin.

PDB = H, Deserializer is enabled and is ON.

Input, LVCMOS

PDB

35

PDB = L, Deserializer is in Power Down mode. When the Deserializer is in Power

w/ pull down

Down. Programmed control register data are NOT retained and reset to default

values.

LOCK Status Output Pin.

Output,

LOCK = H, PLL is Locked, outputs are active

LOCK

34

LVCMOS

LOCK = L, PLL is unlocked, ROUT and PCLK output states are controlled by

OSS_SEL control register. May be used as Link Status.

Reserved.

Pins 38, 39: Route to test point or leave open if unused. See also FPD-LINK III

RES

38, 39, 43, 46

-

INTERFACE pin description section.

Pin 46: This pin MUST be tied LOW.

Pin 43: Leave pin open.

BIST MODE

BIST Enable Pin.

Input, LVCMOS

BISTEN

44

BISTEN = H, BIST Mode is enabled.

w/ pull down

BISTEN = L, BIST Mode is disabled.

PASS Output Pin for BIST mode.

Output,

PASS = H, ERROR FREE Transmission

PASS

37

LVCOMS

PASS = L, one or more errors were detected in the received payload.

Leave Open if unused. Route to test point (pad) recommended.

FPD-LINK III INTERFACE

Input/Output,

Non-inverting differential input, bidirectional control channel output. The interconnect

RIN+

41

CML

must be AC Coupled with a 100 nF capacitor.

Input/Output,

Inverting differential input, bidirectional control channel output. The interconnect must

RIN-

42

CML

be AC Coupled with a 100 nF capacitor.

Non-inverting CML Output

CMLOUTP

38

Output, CML

Monitor point for equalized differential signal. Test port is enabled via control

registers.

Inverting CML Output

CMLOUTN

39

Output, CML

Monitor point for equalized differential signal. Test port is enabled via control

registers.

POWER AND GROUND

SSCG Power, 1.8V ±5%

VDDSSCG

3

Power, Digital

Power supply must be connected regardless if SSCG function is in operation.

LVCMOS I/O Buffer Power, The single-ended outputs and control input are powered

VDDIO1/2/3

29, 20, 7

Power, Digital

VDDD

17

Power, Digital

Digital Core Power, 1.8V ±5%

VDDR

36

Power, Analog

Rx Analog Power, 1.8V ±5%

VDDCML

40

Power, Analog

Bidirectional Channel Driver Power, 1.8V ±5%

VDDPLL

45

Power, Analog

PLL Power, 1.8V ±5%

DAP must be grounded. DAP is the large metal contact at the bottom side, located at

VSS

DAP

Ground, DAP

the center of the WQFN package. Connected to the ground plane (GND) with at least

16 vias.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

6

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