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DS90UB901Q Datasheet(PDF) 10 Page - Texas Instruments |
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DS90UB901Q Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 50 page  DS90UB901Q, DS90UB902Q SNLS322E – JUNE 2010 – REVISED APRIL 2013 www.ti.com Recommended Serializer Timing for PCLK (1) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units tTCP Transmit Clock Period 23.3 T 100 ns tTCIH Transmit Clock Input High 0.4T 0.5T 0.6T ns Time 10 MHz – 43 MHz tTCIL Transmit Clock Input Low 0.4T 0.5T 0.6T ns Time tCLKT PCLK Input Transition Time 0.5 3 ns (Figure 11) fOSC Internal oscillator clock 25 MHz source (1) Recommended Input Timing Requirements are input specifications and not tested in production. Serializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units tLHT CML Low-to-High Transition RL = 100Ω (Figure 6) 150 330 ps Time tHLT CML High-to-Low Transition RL = 100Ω (Figure 6) 150 330 ps Time tDIS Data Input Setup to PCLK 2.0 ns Serializer Data Inputs (Figure 12) tDIH Data Input Hold from PCLK 2.0 ns tPLD Serializer PLL Lock Time RL = 100Ω (1) (2) 1 2 ms tSD RT = 100Ω, PCLK = 10–43 MHz 6.386T + Serializer Delay Register 0x03h b[0] (TRFB = 1) 6.386T + 5 6.386T + 12 ns 19.7 (Figure 14) tJIND Serializer output intrinsic deterministic jitter . Serializer Output Deterministic Measured (cycle-cycle) with 0.13 UI Jitter PRBS-7 test pattern PCLK = 43 MHz(3)(4) tJINR Serializer output intrinsic random Serializer Output Random jitter (cycle-cycle). Alternating-1,0 0.04 UI Jitter pattern. PCLK = 43 MHz(3)(4) tJINT Serializer output peak-to-peak jitter includes deterministic jitter, random jitter, and jitter transfer Peak-to-peak Serializer Output from serializer input. Measured 0.396 UI Jitter (cycle-cycle) with PRBS-7 test pattern. PCLK = 43 MHz(3)(4) λSTXBW Serializer Jitter Transfer PCLK = 43 MHz, Default Registers 1.90 MHz Function -3 dB Bandwidth (Figure 20)(3) δSTX Serializer Jitter Transfer PCLK = 43 MHz, Default Registers 0.944 dB Function (Peaking) (Figure 20)(3) δSTXf Serializer Jitter Transfer PCLK = 43 MHz, Default Registers 500 kHz Function (Peaking Frequency) (Figure 20)(3) (1) tPLD and tDDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK (2) Specification is by design. (3) Typical values represent most likely parametric norms at 1.8V or 3.3V, TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. (4) UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency. 10 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: DS90UB901Q DS90UB902Q |
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