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DS90UB901Q Datasheet(PDF) 4 Page - Texas Instruments |
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DS90UB901Q Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 50 page  DS90UB901Q, DS90UB902Q SNLS322E – JUNE 2010 – REVISED APRIL 2013 www.ti.com DS90UB901Q SERIALIZER PIN DESCRIPTIONS (continued) Pin Name Pin No. I/O, Type Description Input/Output, Data line for the bidirectional control bus communication SDA 5 Open Drain SDA requires an external pull-up resistor to VDDIO. I2C Mode select MODE = L, Master mode (default); Device generates and drives the SCL clock line. Device is connected to slave peripheral on the bus. (Serializer initially starts up in Input, LVCMOS MODE 8 Standby mode and is enabled through remote wakeup by Deserializer) w/ pull down MODE = H, Slave mode; Device accepts SCL clock input and attached to an I2C controller master on the bus. Slave mode does not generate the SCL clock, but uses the clock generated by the Master for the data transfers. Device ID Address Select ID[x] 6 Input, analog Resistor to Ground and 10 k Ω pull-up to 1.8V rail. See Table 3 CONTROL AND CONFIGURATION Power down Mode Input Pin. PDB = H, Serializer is enabled and is ON. Input, LVCMOS PDB 9 PDB = L, Serailizer is in Power Down mode. When the Serializer is in Power Down, w/ pull down the PLL is shutdown, and IDD is minimized. Programmed control register data are NOT retained and reset to default values Input, LVCMOS Reserved. RES 7 w/ pull down This pin MUST be tied LOW. FPD-LINK III INTERFACE Input/Output, Non-inverting differential output, bidirectional control channel input. The interconnect DOUT+ 13 CML must be AC Coupled with a 100 nF capacitor. DOUT- 12 Input/Output, Inverting differential output, bidirectional control channel input. The interconnect must CML be AC Coupled with a 100 nF capacitor. POWER AND GROUND VDDPLL 10 Power, Analog PLL Power, 1.8V ±5% VDDT 11 Power, Analog Tx Analog Power, 1.8V ±5% VDDCML 14 Power, Analog CML & Bidirectional Channel Driver Power, 1.8V ±5% VDDD 28 Power, Digital Digital Power, 1.8V ±5% Power, Digital Power for I/O stage. The single-ended inputs and SDA, SCL are powered from VDDIO. VDDIO 25 VDDIO can be connected to a 1.8V ±5% or 3.3V ±10% Ground, DAP DAP must be grounded. DAP is the large metal contact at the bottom side, located at VSS DAP the center of the WQFN package. Connected to the ground plane (GND) with at least 9 vias. 4 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: DS90UB901Q DS90UB902Q |
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