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DS90UB901Q Datasheet(PDF) 11 Page - Texas Instruments |
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DS90UB901Q Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 50 page  DS90UB901Q, DS90UB902Q www.ti.com SNLS322E – JUNE 2010 – REVISED APRIL 2013 Deserializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Pin/Freq. Min Typ Max Units tRCP Receiver Output Clock Period tRCP = tTCP PCLK 23.3 T 100 ns tPDC Default Registers PCLK Duty Cycle PCLK 45 50 55 % SSCG[3:0] = OFF LVCMOS Low-to-High Transition VDDIO: 1.71V to 1.89V or tCLH 1.3 2.0 2.8 Time 3.0V to 3.6V, CL = 8 pF (lumped load) PCLK ns tCHL LVCMOS High-to-Low Transition Default Registers 1.3 2.0 2.8 Time (Figure 16)(1) LVCMOS Low-to-High Transition VDDIO: 1.71V to 1.89V or tCLH 1.6 2.4 3.3 Time 3.0V to 3.6V, ROUT[13:0], CL = 8 pF (lumped load) ns tCHL HSYNC, VSYNC LVCMOS High-to-Low Transition Default Registers 1.6 2.4 3.3 Time (Figure 16)(1) tROS ROUT Setup Data to PCLK VDDIO: 1.71V to 1.89V or 0.38T 0.5T 3.0V to 3.6V, tROH ROUT[13:0], CL = 8 pF (lumped load) ns HSYNC, VSYNC ROUT Hold Data to PCLK 0.38T 0.5T Default Registers (Figure 18) Default Registers 4.571T 4.571T 4.571T tDD Deserializer Delay Register 0x03h b[0] 10 MHz–43 MHz ns + 8 + 12 + 16 (RRFB = 1) (Figure 17) tDDLT Deserializer Data Lock Time (Figure 15)(2) 10 MHz–43 MHz 10 ms tRJIT (Figure 19, Receiver Input Jitter Tolerance 43 MHz 0.53 UI Figure 21)(3)(4) tRCJ 10 MHz 300 550 PCLK Receiver Clock Jitter ps SSCG[3:0] = OFF(1)(5) 43 MHz 120 250 tDPJ 10 MHz 425 600 PCLK Deserializer Period Jitter ps SSCG[3:0] = OFF(1)(6) 43 MHz 320 480 tDCCJ 10 MHz 320 500 Deserializer Cycle-to-Cycle Clock PCLK ps Jitter SSCG[3:0] = OFF(7)(1) 43 MHz 300 500 fdev Spread Spectrum Clocking ±0.5% to 20 MHz–43 MHz % LVCMOS Output Bus Deviation Frequency ±2.0% SSC[3:0] = ON fmod Spread Spectrum Clocking 9 kHz to (Figure 22) 20 MHz–43 MHz kHz Modulation Frequency 66 kHz (1) Specification is by characterization and is not tested in production. (2) tPLD and tDDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK (3) UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency. (4) tRJIT max (0.61UI) is limited by instrumentation and actual tRJIT of in-band jitter at low frequency (<2 MHz) is greater 1 UI. (5) tDCJ is the maximum amount of jitter measured over 30,000 samples based on Time Interval Error (TIE). (6) tDPJ is the maximum amount the period is allowed to deviate measured over 30,000 samples. (7) tDCCJ is the maximum amount of jitter between adjacent clock cycles measured over 30,000 samples. Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: DS90UB901Q DS90UB902Q |
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