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DS90LV048A

SNLS045C – JULY 1999 – REVISED JULY 2016

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Copyright © 1999–2016, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as

shown in Figure 19. This configuration provides a clean signaling environment for the fast edge rates of the

drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair

cable, a parallel pair cable, or simply PCB traces. Typically, the characteristic impedance of the media is in the

range of 100 Ω. A termination resistor of 100 Ω (selected to match the media) is located as close to the receiver

input pins as possible. The termination resistor converts the driver output (current mode) into a voltage that is

detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects

of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise

margin limits, and total termination loading must be considered.

The DS90LV048A differential line receiver is capable of detecting signals as low as 100 mV, over a ±1-V

common-mode range centered around +1.2 V. This is related to the driver offset voltage which is typically +1.2 V.

The driven signal is centered around this voltage and may shift ±1 V around this center point. The ±1-V shifting

may be the result of a ground potential difference between the ground reference of the driver and the ground

reference of the receiver, the common-mode effects of coupled noise, or a combination of the two. The AC

parameters of both receiver input pins are optimized for a recommended operating input voltage range of 0 V to

The DS90LV048A has a flow-through pinout that allows for easy PCB layout. The LVDS signals on one side of

the device easily allows for matching electrical lengths of the differential pair trace lines between the driver and

the receiver as well as allowing the trace lines to be close together to couple noise as common-mode. Noise

isolation is achieved with the LVDS signals on one side of the device and the TTL signals on the other side.

8.2 Functional Block Diagram