OBSOLETE

DS90CR583, DS90CR584

SNLS110B – JULY 1997 – REVISED APRIL 2013

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Figure 5. DS90CR583 (Transmitter) LVDS Output Load and Transition Times

Figure 6. DS90CR584 (Receiver) CMOS/TTL Output Load and Transition Times

Figure 7. DS90CR583 (Transmitter) Input Clock Transition Time

Note: Measurements at Vdiff = 0V

Note: TCSS measured between earliest and latest LVDS edges.

Note: TxCLK Differential High

→Low Edge

Figure 8. DS90CR583 (Transmitter) Channel-to-Channel Skew and Pulse Width

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