DS90CR483, DS90CR484

SNLS047H – FEBRUARY 2000 – REVISED APRIL 2013

www.ti.com

AC Timing Diagrams

The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.

Figure 1. “Worst Case” Test Pattern

Figure 2. DS90CR483 (Transmitter) LVDS Output Load and Transition Times

Figure 3. DS90CR484 (Receiver) CMOS/TTL Output Load and Transition Times

Figure 4. DS90CR483 (Transmitter) Input Clock Transition Time

Figure 5. DS90CR483 (Transmitter) Setup/Hold and High/Low Times

8

Submit Documentation Feedback

Copyright © 2000–2013, Texas Instruments Incorporated

Product Folder Links: DS90CR483 DS90CR484