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DS90CR485 Datasheet(PDF) 4 Page - Texas Instruments |
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DS90CR485 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 22 page DS90CR485 SNLS143D – FEBRUARY 2003 – REVISED MARCH 2013 www.ti.com Switching Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified. (1) Symbol Parameter Min Typ Max Units TJCC Transmitter Jitter Cycle-to-Cycle (5) f = 133 MHz 40 70 ps f = 100 MHz 45 80 ps f = 66 MHz 50 100 ps BWPLL PLL Bandwidth ≥ 66MHz 600 kHz TPLLS Transmitter Phase Lock Loop Set (Figure 6) 10 ms TPDD Transmitter Powerdown Delay (Figure 7) 100 ns TPDL Transmitter Input to Output Latency (Figure 8) 6(TCIP) 7(TCIP) 8(TCIP) ns (5) The limits are based on bench characterization of the device's jitter response over the power supply voltage range. Output clock jitter is measured with a cycle-to-cycle jitter of ±10% at a 1µs rate applied to the transmitter’s input clock signal (CLKIN) while data inputs are switching with internal PRBS generator enabled without DC-Balance. The typical data is measured with a cycle-to-cycle jitter of ±100ps applied to the transmitter’s input clock signal (CLKIN). 4 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: DS90CR485 |
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Similar Description - DS90CR485_15 |
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