DS90CR218A

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SNLS054D – NOVEMBER 1999 – REVISED APRIL 2013

DS90CR218A +3.3V Rising Edge Data Strobe LVDS

21-Bit Channel Link - 12 MHz to 85 MHz

Check for Samples: DS90CR218A

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FEATURES

DESCRIPTION

•

12 to 85 MHz Shift Clock Support

The DS90CR218A receiver deserializes three input

•

50% Duty Cycle on Receiver Output Clock

LVDS data streams into 21 bits of CMOS/TTL output

•

Low Power Consumption

data. When operating at the maximum input clock

rate of 85 Mhz, the LVDS data is received at 595

•

±1V Common-mode Range (Around +1.2V)

Mbps per data channel for a total data throughput of

•

Narrow Bus Reduces Cable Size and Cost

1.785 Gbit/sec (233 Mbytes/sec).

•

Up to 1.785 Gbps Throughput

The

narrow

bus

and

LVDS

signalling

of

the

•

Up to 223 Mbytes/sec Bandwidth

DS90CR218A is an ideal means to solve EMI and

•

345 mV (typ) Swing LVDS Devices for Low EMI

cable size problems associated with wide, high-speed

TTL interfaces.

•

PLL Requires No External Components

•

Rising Edge Data Strobe

•

Compatible with TIA/EIA-644 LVDS Standard

•

Low Profile 48-Lead TSSOP Package

Block Diagram

Figure 1. DS90CR218A Top View

See Package Number DGG-48 (TSSOP)

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PRODUCTION DATA information is current as of publication date.

Copyright © 1999–2013, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.