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DP83910A Datasheet(PDF) 8 Page - National Semiconductor (TI) |
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DP83910A Datasheet(HTML) 8 Page - National Semiconductor (TI) |
8 / 12 page 90 Switching Characteristics (Continued) Transmit Timing (End of Packet) TLF9365 – 5 Transmit Specifications (End of Packet) Symbol Parameter Min Max Units tTXEh Transmit Enable Hold Time from Rising Edge of TXC 0 ns tTOh Transmit Output High before Idle (Half Step) 200 ns tTOi Transmit Output Idle Time (Half Step) 8000 ns Receive Timing (Start of Packet) TLF9365 – 6 Receiver Specifications (Start of Packet) Symbol Parameter Min Max Units tRCd Receive Clock Duty Cycle (Note 1) 40 60 % tRCr Receive Clock Rise Time (20% to 80% CTL e 30 pF) 7 ns tRCf Receive Clock Fall Time (80% to 20% CTL e 30 pF) 7 ns tCRSon Carrier Sense Turn On Delay 70 ns tDAT Decoder Acquisition Time 700 ns tRDd Receive Data Output Delay 150 ns tRDs Receive Data Output Stable after Going Valid 90 ns tDtor Differential Inputs Turn-On Pulse (Note 2) 30 ns tRDV Receive Data Output Valid from Falling Edge of RXC 10 ns Note 1 This parameter is measured using the fifty percent point of each clock edge Note 2 This parameter was characterized with a differential input of b375 mV on the receive pair inputs 8 |
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Similar Description - DP83910A |
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