DS90C365A

SNLS181I – APRIL 2004 – REVISED APRIL 2013

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Transmitter Switching Characteristics (continued)

Over recommended operating supply and temperature ranges unless otherwise specified

Symbol

Parameter

Min

Typ

Max

Unit

TPPos0

−0.25

0

+0.25

ns

TPPos1

Transmitter Output Pulse Position

3.32

3.57

3.82

ns

TPPos2

Transmitter Output Pulse Position

6.89

7.14

7.39

ns

TPPos3

Transmitter Output Pulse Position

10.46

10.71

10.96

ns

TPPos4

Transmitter Output Pulse Position

14.04

14.29

14.54

ns

TPPos5

Transmitter Output Pulse Position

17.61

17.86

18.11

ns

TPPos6

Transmitter Output Pulse Position

21.18

21.43

21.68

ns

TPPos0

−0.20

0

+0.20

ns

TPPos1

Transmitter Output Pulse Position

2.00

2.20

2.40

ns

TPPos2

Transmitter Output Pulse Position for Bit 2

4.20

4.40

4.60

ns

TPPos3

Transmitter Output Pulse Position for Bit 3

6.39

6.59

6.79

ns

TPPos4

Transmitter Output Pulse Position

8.59

8.79

8.99

ns

TPPos5

Transmitter Output Pulse Position

10.79

10.99

11.19

ns

TPPos6

Transmitter Output Pulse Position

12.99

13.19

13.39

ns

TPPos0

−0.20

0

+0.20

ns

TPPos1

Transmitter Output Pulse Position

1.48

1.68

1.88

ns

TPPos2

Transmitter Output Pulse Position

3.16

3.36

3.56

ns

TPPos3

Transmitter Output Pulse Position

4.84

5.04

5.24

ns

TPPos4

Transmitter Output Pulse Position

6.52

6.72

6.92

ns

TPPos5

Transmitter Output Pulse Position

8.20

8.40

8.60

ns

TPPos6

Transmitter Output Pulse Position

9.88

10.08

10.28

ns

TSTC

Required TxIN Setup to TxCLK IN

2.5

ns

(Figure 6) at 85MHz

THTC

Required TxIN Hold to TxCLK IN (Figure 6) at

0.5

ns

87.5 MHz

TCCD

TxCLK IN to TxCLK OUT Delay. Measure from

3.086

7.211

ns

TxCLK IN edge to immediatley crossing poing

of differential TxCLK OUT by following the

= 70°C, and

postive TxCLK OUT. 50% duty cycle input

25MHz for "Max",

clock is assumed. (Figure 7)

pin = VCC

Measure from TxCLK IN edge to immediatley

2.868

6.062

ns

crossing poing of differential TxCLK OUT by

following the postive TxCLK OUT. 50% duty

= 70°C, and

cycle input clock is assumed. (Figure 8)

25MHz for "Max",

pin = GND

SSCG

Spread Spectrum Clock support; Modulation

f = 25 MHz

100kHz ±

2.5%/

−5%

f = 40 MHz

100kHz ±

2.5%/

−5%

f = 65 MHz

100kHz ±

2.5%/

−5%

f = 87.5 MHz

100kHz ±

2.5%/

−5%

TPLLS

Transmitter Phase Lock Loop Set (Figure 9)

10

ms

TPDD

Transmitter Power Down Delay (Figure 11)

100

ns

(2)

Care must be taken to ensure TSTC and THTC are met so input data are sampling correctly. This SSCG parameter only shows the

performance of tracking Spread Spectrum Clock applied to TxCLK IN pin, and reflects the result on TxCLKOUT+ and TxCLKOUT

− pins.

4

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