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DS90C187 Datasheet(PDF) 9 Page - Texas Instruments |
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DS90C187 Datasheet(HTML) 9 Page - Texas Instruments |
9 / 28 page f f / 16 f / 8 f / 4 f / 2 Steady State, Low Steady State, Low f / 16 f / 8 f / 4 f / 2 Steady State, Low Steady State, Low f / 16 f / 8 f / 4 f / 2 Steady State, Low Steady State, Low Steady State, High Steady State, High Steady State, High PCLK R0 R1 R2 R3 R4 R5 G0 G1 G2 G3 G4 G5 B0 B1 B2 B3 B4 B5 HS VS DE Signal Signal Pattern Signal Frequency T IN_CLK INn_x, n = A or B, x = ODD INn_x, n = A or B, x = EVEN Falling Edge CLK (RFB = GND) shown DS90C187 www.ti.com SNLS401B – FEBRUARY 2012 – REVISED APRIL 2013 AC Timing Diagrams A. The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVCMOS/ I/O. B. Figure 2 and Figure 3 show a falling edge data strobe (IN_CLK). Figure 2. Checker Board Test Pattern A. The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVCMOS/ I/O. B. Recommended pin to signal mapping for 18 bits per pixel, customer may choose to define differently. The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical stripes across the display. C. Figure 2 and Figure 3 show a falling edge data strobe (IN_CLK). Figure 3. “16 Gray Scale” Test Pattern (Falling Edge Clock shown) Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: DS90C187 |
Similar Part No. - DS90C187_14 |
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Similar Description - DS90C187_14 |
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