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DS80PCI810NJYR Datasheet(PDF) 6 Page - Texas Instruments |
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DS80PCI810NJYR Datasheet(HTML) 6 Page - Texas Instruments |
6 / 60 page DS80PCI810 SNLS493A – OCTOBER 2014 – REVISED JANUARY 2015 www.ti.com Pin Functions(1) (continued) PIN NAME PIN NUMBER I/O, TYPE DESCRIPTION I, 4-LEVEL, Reserved RESERVED3 19 LVCMOS This input must be tied via external 1 k Ω to GND. CONTROL PINS — BOTH PIN AND SMBUS MODES (LVCMOS) The RXDET pin controls the RX detection function. Depending on the I, 4-LEVEL, input level, a 50 Ω or >50 kΩ termination to the power rail is enabled. RXDET 22 LVCMOS Keep this input floating for normal PCIe operation. See Table 2. I, 4-LEVEL, Reserved RESERVED1 23 LVCMOS This input must be left floating. Controls the internal regulator Float = 2.5 V mode VDD_SEL 25 I, FLOAT Tie to GND = 3.3 V mode See Figure 31. Tie High = Low power - Power Down PWDN 52 I, LVCMOS Tie to GND = Normal Operation See Table 2. Valid Register Load Status Output ALL_DONE 27 O, LVCMOS HIGH = External EEPROM load failed or incomplete LOW = External EEPROM load passed POWER In 3.3 V mode, feed 3.3 V to VIN VIN 24 Power In 2.5 V mode, leave floating. Power Supply for CML and Analog Pins In 2.5 V mode, connect to 2.5 V VDD 9, 14, 36, 41, 51 Power In 3.3 V mode, connect 0.1 µF cap to each VDD Pin and GND See Figure 31 for proper power supply decoupling . GND DAP Power Ground pad (DAP - die attach pad). 6 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated |
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