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DS80PCI402 Datasheet(PDF) 5 Page - Texas Instruments |
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DS80PCI402 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 54 page  DS80PCI402 www.ti.com SNLS324E – APRIL 2011 – REVISED JANUARY 2015 Pin Functions(1)(2)(3)(4) (continued) PIN I/O, TYPE DESCRIPTION NAME NUMBER O, 2- Valid register load status output ALL_DONE 27 LEVEL, HIGH = External EEPROM load failed or incomplete LVCMOS LOW = External EEPROM load passed ENSMB = 0 (PIN MODE) EQA[1:0] and EQB[1:0] control the level of equalization on the input pins. The pins are active only when ENSMB is deasserted (low). The 8 channels are organized into two EQA0, EQA1, 20, 19, 46, I, 4-LEVEL, banks. Bank A is controlled with the EQA[1:0] pins and bank B is controlled with the EQB0, EQB1 47 LVCMOS EQB[1:0] pins. When ENSMB goes high the SMBus registers provide independent control of each channel. The EQB[1:0] pins are converted to SMBUS AD2/AD3 inputs. See Table 2. DEMA[1:0] and DEMB[1:0] control the level of de-emphasis of the output driver. The pins are only active when ENSMB is deasserted (low). The 8 channels are organized into two banks. Bank A is controlled with the DEMA[1:0] pins and bank B is controlled DEMA0, DEMA1, 49, 50, 53, I, 4-LEVEL, with the DEMB[1:0] pins. When ENSMB goes high the SMBus registers provide DEMB0, DEMB1 54 LVCMOS independent control of each channel. The DEMA[1:0] pins are converted to SMBUS SCL/SDA and DEMB[1:0] pins are converted to AD0, AD1 inputs. See Table 3. CONTROL PINS — BOTH PIN AND SMBUS MODES (LVCMOS) RATE control pin selects GEN 1,2 and GEN 3 operating modes. Tie 1 k Ω to GND = GEN 1,2 I, 4-LEVEL, RATE 21 FLOAT = AUTO Rate Select of Gen1/2 and Gen3 with de-emphasis LVCMOS Tie 20 k Ω to GND = GEN 3 without de-emphasis Tied 1 k Ω to VDD = RESERVED The RXDET pin controls the receiver detect function. Depending on the input level, a 50- I, 4-LEVEL, RXDET 22 Ω or > 50-kΩ termination to the power rail is enabled. LVCMOS See Table 4. Controls the loopback function I, 4-LEVEL, Tie 1 k Ω to GND = Root Complex Loopback (INA_n to OUTB_n) LPBK 23 LVCMOS Float = Normal Operation Tie 1 k Ω to VDD = End-point Loopback (INB_n to OUTA_n) Controls the internal regulator FLOAT = 2.5-V mode VDD_SEL 25 I, LVCMOS Tie GND = 3.3-V mode See Figure 14. I, 4-LEVEL, Controls the internal Signal Detect Threshold. SD_TH 26 LVCMOS See Table 5. Cable Present Detect input. High when a cable is not present per PCIe Cabling Spec. I, 2-LEVEL, PRSNT 52 1.0. Puts part into low power mode. When LOW (normal operation) part is enabled. LVCMOS See Table 4. POWER In 3.3-V mode, feed 3.3 V to VIN VIN 24 Power In 2.5-V mode, leave floating Power supply pins 9, 14, 36, VDD Power 2.5-V mode, connect to 2.5-V supply 41, 51 3.3-V mode, connect 0.1-µF capacitor to each VDD pin (output of LDO) GND DAP Power Ground pad (DAP - die attach pad) Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: DS80PCI402 |
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