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CY74FCT841CTSOCTE4 Datasheet(PDF) 1 Page - Texas Instruments

Part # CY74FCT841CTSOCTE4
Description  10-BIT LATCHES WITH 3-STATE OUTPUTS
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CY74FCT841CTSOCTE4 Datasheet(HTML) 1 Page - Texas Instruments

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CY54FCT841T, CY74FCT841T
10-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS035A – SEPTEMBER 1994 – REVISED OCTOBER 2001
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Function, Pinout, and Drive Compatible
With FCT, F, and AM29841 Logic
D Reduced VOH (Typically = 3.3 V) Versions of
Equivalent FCT Functions
D Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
D Ioff Supports Partial-Power-Down Mode
Operation
D Matched Rise and Fall Times
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D Fully Compatible With TTL Input and
Output Logic Levels
D High-Speed Parallel Latches
D Buffered Common Latch-Enable Input
D 3-State Outputs
D CY54FCT841T
– 32-mA Output Sink Current
– 12-mA Output Source Current
D CY74FCT841T
– 64-mA Output Sink Current
– 32-mA Output Source Current
description
The ’FCT841T bus-interface latches are designed to eliminate additional packages required to buffer existing
latches and provide additional data width for wider address/data paths or buses carrying parity. The ’FCT841T
devices are buffered 10-bit-wide versions of the FCT373 function.
The ’FCT841T devices’ high-performance interface is designed for high-capacitance-load drive capability, while
providing low-capacitance bus loading at both inputs and outputs. Outputs are designed for low-capacitance
bus loading in the high-impedance state.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered down.
PIN DESCRIPTION
NAME
I/O
DESCRIPTION
D
I
Latch data inputs
LE
I
Latch-enable input. The latches are transparent when LE is high.
Input data is latched on the high-to-low transition.
Y
O
3-state latch outputs
OE
I
Output-enable control. When OE is low, the outputs are enabled.
When OE is high, the outputs are in the high-impedance (off) state.
Copyright
 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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10
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24
23
22
21
20
19
18
17
16
15
14
13
OE
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
GND
VCC
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
LE
CY54FCT841T ...D PACKAGE
CY74FCT841T ...P, Q, OR SO PACKAGE
(TOP VIEW)
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.


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