CY54FCT841T, CY74FCT841T

10-BIT LATCHES

WITH 3-STATE OUTPUTS

SCCS035A – SEPTEMBER 1994 – REVISED OCTOBER 2001

5

POST OFFICE BOX 655303

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted) (continued)

PARAMETER

TEST CONDITIONS

CY54FCT841T

CY74FCT841T

UNIT

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

MIN

TYP†

MAX

UNIT

#

VCC =5 5V

One bit switching

at f1 = 10 MHz

VIN ≤ 0.2 V or

VIN ≥ VCC – 0.2 V

0.7

1.4

#

VCC = 5.5 V,

Outputs open,

1

at 50% duty cycle

VIN = 3.4 V or GND

1

2.4

#

,

OE = GND,

LE = VCC

10 bits switching

at f1 = 2.5 MHz

VIN ≤ 0.2 V or

VIN ≥ VCC – 0.2 V

1

3.2||

IC#

1

at 50% duty cycle

VIN = 3.4 V or GND

4.1

13.2||

mA

IC#

VCC = 5 25 V

One bit switching

at f1 = 10 MHz

VIN ≤ 0.2 V or

VIN ≥ VCC – 0.2 V

0.7

1.4

mA

VCC = 5.25 V,

Outputs open,

1

at 50% duty cycle

VIN = 3.4 V or GND

1

2.4

,

OE = GND,

LE = VCC

10 bits switching

at f1 = 2.5 MHz

VIN ≤ 0.2 V or

VIN ≥ VCC – 0.2 V

1

3.2||

1

at 50% duty cycle

VIN = 3.4 V or GND

4.1

13.2||

Ci

5

10

5

10

pF

Co

9

12

9

12

pF

† Typical values are at VCC = 5 V, TA = 25°C.

# IC

= ICC + ∆ICC × DH × NT + ICCD (f0/2 + f1 × N1)

Where:

IC

= Total supply current

ICC

= Power-supply current with CMOS input levels

∆ICC = Power-supply current for a TTL high input (VIN = 3.4 V)

DH

= Duty cycle for TTL inputs high

NT

= Number of TTL inputs at DH

ICCD = Dynamic current caused by an input transition pair (HLH or LHL)

f0

= Clock frequency for registered devices, otherwise zero

f1

= Input signal frequency

N1

= Number of inputs changing at f1

All currents are in milliamperes and all frequencies are in megahertz.

|| Values for these conditions are examples of the ICC formula.

timing requirements over recommended operating free-air temperature range (unless otherwise

noted) (see Figure 1)

CY54FCT841AT

CY74FCT841AT

CY74FCT841BT

CY74FCT841CT

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

tw

Pulse duration, LE high

5

4

4

4

ns

tsu

Setup time, data before LE

↑

2.5

2.5

2.5

2.5

ns

th

Hold time, data after LE

↑

3

2.5

2.5

2.5

ns