CY29FCT520T

MULTILEVEL PIPELINE REGISTER

WITH 3-STATE OUTPUTS

SCCS011C – MAY 1994 – REVISED NOVEMBER 2001

1

POST OFFICE BOX 655303

With FCT, F Logic, and AM29520

Equivalent FCT Functions

Significantly Improved Noise

Characteristics

Operation

Output Logic Levels

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

– 64-mA Output Sink Current

32-mA Output Source Current

– 32-mA Output Sink Current

12-mA Output Source Current

description

The CY29FCT520T is a multilevel 8-bit-wide pipeline register. The device consists of four registers, A1, A2, B1,

pipelines. The contents of any register can be read at the multiplexed output at any time by using the

The pipeline registers are positive-edge triggered, and data is shifted by the rising edge of the clock input.

Instruction I = 0 selects the four-level pipeline mode. Instruction I = 1 selects the two-level B pipeline, while I = 2

selects the two-level A pipeline. I = 3 is the hold instruction; no shifting is performed by the clock in this mode.

In the two-level operation mode, data is shifted from level 1 to level 2 and new data is loaded into level 1.

preventing damaging current backflow through the device when it is powered down.

Copyright

 2001, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

CLK

GND

D, P, OR SO PACKAGE

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On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.