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DP83907 Datasheet(PDF) 62 Page - National Semiconductor (TI) |
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DP83907 Datasheet(HTML) 62 Page - National Semiconductor (TI) |
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62 / 70 page  Preliminary Switching Design Guidelines Memory Support Bus Accesses (for IO port or FIFO transfers) TLF12082 – 44 MEMORY SUPPORY BUS ACCESSES (for IO Port or FIFO Transfers) Symbol Description 8-Bit Transfers 16-Bit Transfers Units Min Max Min Max T1 MSA1–13 Valid before RCS 30 30 ns Asserted T2 MSA1–13 Valid before 20 20 ns MSRD–WR Asserted T3 MSRD–WR Width 70 70 ns T4 RCS Valid to MSWR or MSRD Deasserted 105 105 ns T5 MSA1–13 Valid after 10 10 ns MSRD–WR Deasserted T6 RCS Held after MSRD–WR 10 10 ns Deasserted T7 RCS Active to MSD(015) Valid 100 100 ns T8 Read Data Hold from MSRD Deasserted 0 0 ns T9 Write Data Set-Up to MSWR Deasserted 40 40 ns T10 Write Data Hold from MSWR Deasserted 10 10 ns 62 |
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