10

11

12

36

35

34

33

32

31

30

29

28

27

26

25

1

2

3

4

5

6

7

8

9

DAP = GND

DS34RT5110

(Top View)

D_IN2+

D_IN2-

D_IN1+

D_IN1-

D_IN0+

D_IN0-

C_IN+

C_IN-

D_OUT2+

D_OUT2-

D_OUT1+

D_OUT1-

D_OUT0+

D_OUT0-

C_OUT+

C_OUT-

VDD

VDD

VDD

VDD

GND

GND

GND

GND

DS34RT5110

www.ti.com

SNLS310G – MARCH 2009 – REVISED APRIL 2013

PIN DESCRIPTIONS (continued)

Pin Name

Pin Number

I/O, Type

Description

LOCK

14

O, LVCMOS

Lock Indicator Output pin.

H = PLL is locked.

L = PLL is not locked.

VOD_CRL

48

I,

VOD control pin. Refer to Table 3. See Functional Description.

Analog

External resistance = 24 k

Ω to GND, Output DC Coupled Application.

External resistance = 12 k

Ω to GND, Output AC Coupled Application.

LFp

40

I,

Loop filter capacitor pins.

LFn

41

Analog

See Functional Description.

Power

3, 6, 7,

Power

10, 13,

15, 46

POWER SUPPLY BYPASSING for additional details.

GND

22, 24,

GND

Ground reference. GND should be tied to a solid ground plane through a low impedance

27, 30,

path.

31, 34

Exposed

DAP

GND

Ground reference. The exposed pad at the center of the package must be connected to the

DAP

ground plane.

Other

Reserv

16, 17,

Reserved. Do not connect. Leave open.

18, 19,

20, 23

Connection Diagram

TOP VIEW — Not to Scale

48 Pin WQFN Package

See Package Number RHS0048A

Copyright © 2009–2013, Texas Instruments Incorporated

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