DS90CF363B

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SNLS180D – JULY 2004 – REVISED APRIL 2013

The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.

The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern

approximates signal switching needed to produce groups of 16 vertical stripes across the display.

Figure 2 and Figure 3 show a falling edge data strobe (TxCLK IN/RxCLK OUT).

Recommended pin to signal mapping. Customer may choose to define differently.

Figure 3. “16 Grayscale” Test Pattern

Figure 4. DS90CF363B (Transmitter) LVDS Output Load

Figure 5. DS90CF363B (Transmitter) LVDS Transition Times

Figure 6. DS90CF363B (Transmitter) Input Clock Transition Time

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