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DP83901 Datasheet(PDF) 61 Page - National Semiconductor (TI) |
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DP83901 Datasheet(HTML) 61 Page - National Semiconductor (TI) |
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61 / 62 page  150 Switching Characteristics AC Specs DP83901A Note All Timing is Preliminary (Continued) Transmit Timing (End of Packet) TLF10469 – 47 TRANSMIT SPECIFICATIONS (End of Packet) Symbol Parameter Min Max Units tTOH Transmit Output High before Idle (Half Step) 200 ns tTOI Transmit Output Idle Time to g40 mV(Half Step) 8000 ns Reset Timing TLF10469 – 45 Symbol Parameter Min Max Units rstw Reset Pulse Width (Note 1) 8 BSCK Cycles or TXC Cycles (Note 2) Note 1 The RESET pulse requires the BSCK and TXC be stable On power up RESET should not be raised until BSCK and TXC have become stable Several registers are affected by RESET Consult the register descriptions for details Note 2 The slower of BSCK or TXC clocks will determine the minimum time for the RESET signal to be low TXC is X1 divided by 2 If BSCK k TXC then RESET e 8 c BSCK If TXC k BSCK then RESET e 8 c TXC 160 AC Timing Test Conditions All specifications are valid only if the mandatory isolation is employed and all differential signals are taken to be at the AUI side of the pulse transformer Input Pulse Levels (TTLCMOS) GND to 30V Input Rise and Fall Times (TTLCMOS) 5 ns Input and Output Reference Levles (TTLCMOS) 13V Input Pulse Levels (Diff) b 350 mV to b1315 mV Input and Output 50% Point of Reference Levels (Diff) the Differential TRI-STATE Reference Levels Float (DV) g05V Output Load (See Figure Below) TLF10469 – 48 Note 1 50 pF includes scope and jig capacitance Note 2 S1 e Open for timing tests for push pull outputs S1 e VCC for VOL test S1 e GND for VOH test S1 e VCC for High Impedance to active low and active low to High Impedance measurements S1 e GND for High Impedance to active high and active high to High Impedance measurements 61 |
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Similar Description - DP83901 |
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