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DRA754 Datasheet(PDF) 9 Page - Texas Instruments |
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DRA754 Datasheet(HTML) 9 Page - Texas Instruments |
9 / 443 page Copyright © 2015–2016, Texas Instruments Incorporated Device Comparison Submit Documentation Feedback Product Folder Links: DRA744 DRA745 DRA746 DRA750 DRA751 DRA752 DRA754 DRA755 DRA756 9 DRA744, DRA745, DRA746 DRA750, DRA751, DRA752 DRA754, DRA755, DRA756 www.ti.com SPRS950A – DECEMBER 2015 – REVISED APRIL 2016 Table 3-1. Device Comparison (continued) Features Device Jacinto 6 EX Jacinto 6 EP Jacinto 6 DRA756 DRA755 DRA754 DRA752 DRA751 DRA750 DRA746 DRA745 DRA744 Universal Serial Bus (USB3.0) USB1 (SuperSpeed, Dual-Role-Device [DRD]) Yes Yes Yes Universal Serial Bus (USB2.0) USB2 (HighSpeed, Dual-Role-Device [DRD], with embedded HS PHY) Yes Yes Yes USB3 (HighSpeed, OTG2.0, with ULPI) Yes Yes Yes USB4 (HighSpeed, OTG2.0, with ULPI) Yes Yes Yes(1) (1) USB4 will not be supported on some pin-compatible roadmap devices. USB3 will be mapped to these balls instead. Pin compatibility can be maintained in the future by either not using USB4, or via software change to use USB4 on this device, but USB3 on these balls in the future. (2) In the Unified L3 memory map, there is maximum of 2GB of SDRAM space which is available to all L3 initiators including MPU (MPU, GPU, DSP, IVA, DMA, etc). Typically this space is interleaved across both EMIFs to optimize memory performance. If a system populates > 2GB of physical memory, that additional addressable space can be accessed only by the MPU via the ARM V7 Large Physical Address Extensions (LPAE). 3.2 Related Products Automotive Processors DRAx Infotainment SoCs The "Jacinto 6" family of infotainment processors (DRA7xx), paired with robust software and ecosystem offering bring unprecedented feature-rich, in-vehicle infotainment, instrument cluster and telematics features to the next generation automobiles. |
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