DRV590

SLOS365A – AUGUST 2001 – REVISED AUGUST 2002

11

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APPLICATION INFORMATION

LC filter in the time domain (continued)

For worst case conditions, the on-resistance of the output transistors has been ignored to give the maximum

theoretical ripple current. In reality, the voltage drop across the output transistors will decrease the maximum

current, and therefore the TEC ripple current.

general operation

The onboard ramp generator requires an external resistor and capacitor to set the oscillation frequency. For

ceramic 220 pF with 10% tolerance. Both components should be grounded to AGND, which should be

connected to PGND at a single point, typically where the power and ground physically connect to the printed

circuit board.

AREF capacitor

The AREF terminal is the output of an internal mid-rail voltage regulator used for the on-board oscillator and

ramp generator. The regulator may not be used to provide power to any additional circuitry. A 1-

µF ceramic

section for AGND connection information).

gain settings

The differential output voltage may be calculated using equation 7.

V

O +

V

OUT

)

–V

OUT– +

Av V

IN

)

–V

IN–

Av is the voltage gain, which may be selected by configuring GAIN0 and GAIN1 according to the table below.

The input resistance also varies with the gain setting, as shown by the typical values in Table 1. Though these

values may vary by up to 30% due to process variations, the gain settings themselves vary little, as they are

determined by resistor ratios.

Table 1. Gain Settings

GAIN0

GAIN1

AMPLIFIER GAIN

(dB, TYPICAL)

INPUT RESISTANCE

(k

Ω, TYPICAL)

0

0

6

104

0

1

12

74

1

0

18

44

1

1

23.5

24

(7)