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DP83867IRRGZR Datasheet(PDF) 6 Page - Texas Instruments |
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DP83867IRRGZR Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 132 page  6 DP83867IR, DP83867CR SNLS484D – FEBRUARY 2015 – REVISED JULY 2016 www.ti.com Product Folder Links: DP83867IR DP83867CR Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Changes from Original (February 2015) to Revision A Page • Changed the document title From: "Robust, Low Power" To: "Robust, High Immunity" ....................................................... 1 • Changed the Features listed under "Highlights" .................................................................................................................... 1 • Changed the Applications list ................................................................................................................................................ 1 • Changed the Description text and layout .............................................................................................................................. 1 • Added TF fall time = 0.75 ns (Max) in RGMII Timing (4) ........................................................................................................ 19 • Added T4, MDI to GMII Latency = 264 ns (NOM) to GMII Receive Timing (6). .................................................................... 22 • Changed the title of Figure 21 From: Typical MDC/MDIO Read Operation To: Fast Link Drop Mechanism....................... 43 • Moved text From the end of Table 11 To PHY Identifier Register #1 (PHYIDR1) .............................................................. 59 • Changed format of loopback control bits in Table 31 "BIST Control Register (BISCR)" .................................................... 77 • Changed BIT NAME (11:8) From: "LED_ACT_SEL To: LED_2_SEL in Table 33 .............................................................. 80 • Changed BIT NAME (7:4) From: "LED_SPD_SEL To: LED_1_SEL in Table 33 ............................................................... 81 • Changed BIT NAME (3:0 From: "LED_LNK_SEL To: LED_0_SEL in Table 33 ................................................................. 81 • Changed the title of Table 45 from: Address 0x006FE to: Address 0x006F ....................................................................... 90 • Changed default of bits 12:8 to 0 1100 in I/O Configuration (IO_MUX_CFG), Address 0x0170 ....................................... 102 • Deleted text "of the 64-QFP package" from the second paragraph in section Cable Line Driver...................................... 114 • Deleted text "for MII Mode" from the second paragraph in section Clock In (XI) Recommendation ................................. 115 |
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