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DP83867IRPAPT Datasheet(PDF) 11 Page - Texas Instruments |
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DP83867IRPAPT Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 132 page  11 DP83867IR, DP83867CR www.ti.com SNLS484D – FEBRUARY 2015 – REVISED JULY 2016 Product Folder Links: DP83867IR DP83867CR Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Table 2. Pin Functions (continued) PIN TYPE(1) DESCRIPTION NAME NUMBER PAP RGZ General Purpose I/O GPIO_0 39 S, O, PD General Purpose I/O: This signal provides a multi-function configurable I/O. Please refer to the GPIO_MUX_CTRL register for details. GPIO_1 40 S, O, PD General Purpose I/O: This signal provides a multi-function configurable I/O. Please refer to the GPIO_MUX_CTRL register for details. MANAGEMENT INTERFACE MDC 20 16 I, PD MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO serial management input/output data. This clock may be asynchronous to the MAC transmit and receive clocks. The maximum clock rate is 25MHz and no minimum. MDIO 21 17 I/O MANAGEMENT DATA I/O: Bi-directional management instruction/data signal that may be sourced by the management station or the PHY. This pin requires pullup resistor. The IEEE specified resistor value is 1.5kΩ, but a 2.2kΩ is acceptable. INT / PWDN 60 44 I/O, PU INTERRUPT / POWER DOWN: The default function of this pin is POWER DOWN. POWER DOWN: Asserting this signal low enables the Power Down mode of operation. In this mode, the device will power down and consume minimum power. Register access will be available through the Management Interface to configure and power up the device. INTERRUPT: This pin may be programmed as an interrupt output instead of a Powerdown input. In this mode, Interrupts will be asserted low using this pin. Register access is required for the pin to be used as an interrupt mechanism. When operating this pin as an interrupt, an external 2.2kΩ connected to the VDDIO supply is recommended. RESET RESET_N 59 43 I, PU RESET: The active low RESET initializes or re-initializes the DP83867. All internal registers will re-initialize to their default state upon assertion of RESET. The RESET input must be held low for a minimum of 1µs. CLOCK INTERFACE XI 19 15 I CRYSTAL/OSCILLATOR INPUT: 25 MHz oscillator or crystal input (50 ppm) XO 18 14 O CRYSTAL OUTPUT: Second terminal for 25 MHz crystal. Must be left floating if a clock oscillator is used. CLK_OUT 22 18 O CLOCK OUTPUT: Output clock JTAG INTERFACE JTAG_CLK 25 20 I, PU JTAG TEST CLOCK: IEEE 1149.1 Test Clock input, primary clock source for all test logic input and output controlled by the testing entity. JTAG_TDO 26 21 O JTAG TEST DATA OUTPUT: IEEE 1149.1 Test Data Output pin, the most recent test results are scanned out of the device via TDO. JTAG_TMS 27 22 I, PU JTAG TEST MODE SELECT: IEEE 1149.1 Test Mode Select pin, the TMS pin sequences the Tap Controller (16-state FSM) to select the desired test instruction. JTAG_TDI 28 23 I, PU JTAG TEST DATA INPUT: IEEE 1149.1 Test Data Input pin, test data is scanned into the device via TDI. JTAG_TRSTN 24 I, PU JTAG TEST RESET: IEEE 1149.1 Test Reset pin, active low reset provides for asynchronous reset of the Tap Controller. This reset has no effect on the device registers. |
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