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DRA658 Datasheet(PDF) 2 Page - Texas Instruments |
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DRA658 Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 7 page  DRA64x, DRA65x SPRT656 – JANUARY 2013 www.ti.com – Advanced Video Processing Features Such • One System Watchdog Timer (WDT 0) as Scan/Format/Rate Conversion • Six Configurable UART/IrDA/CIR Modules – Three Graphics Layers and Compositors – UART0 With Modem Control Signals • Dual 32-bit DDR2/DDR3 SDRAM Interfaces – Supports up to 3.6864 Mbps UART0/1/2 – Supports up to DDR2-800 and DDR3-800 – Supports up to 12 Mbps UART3 – Up to Eight x 8 Devices Total 2 GB Total – SIR, MIR, FIR (4.0 MBAUD), and CIR Address Space • Four Serial Peripheral Interfaces (SPIs) [up to – Dynamic Memory Manager (DMM) 48-MHz] • Programmable Multi-Zone Memory – Each With Four Chip-Selects Mapping and Interleaving • Three MMC/SD/SDIO Serial Interfaces [up to 48- • Enables Efficient 2D Block Accesses MHz] • Supports Tiled Objects in 0°, 90°, 180°, or – Three Supporting up to 1-/4-/8-Bit Modes 270° Orientation and Mirroring • Dual Controller Area Network (DCAN) Modules • Optimizes Interlaced Accesses – CAN Version 2 Part A, B • General Purpose Memory Controller (GPMC) • Four Inter-Integrated Circuit (I2C Bus™) Ports – 8-/16-bit Multiplexed Address/Data Bus • Six Multi-Channel Audio Serial Ports (McASP) – 512M-Byte Total Address Space Divided – Dual Ten Serializer Transmit/Receive Ports Among up to 8 Chip Selects – Quad Four Serializer Transmit/Receive Ports – Glueless Interface to NOR Flash, NAND – DIT-Capable For S/PDIF (All Ports) Flash (BCH/Hamming Error Code Detection), • Multi-Channel Buffered Serial Port (McBSP) SRAM and Pseudo-SRAM – Transmit/Receive Clocks up to 48 MHz – Error Locator Module (ELM) Outside of – Two Clock Zones and Two Serial Data Pins GPMC to Provide Upto 16-Bit/512-Bytes – Supports TDM, I2S, and Similar Formats Hardware ECC for NAND • Serial ATA (SATA) 3.0 Gbps Controller With – Flexible Asynchronous Protocol Control for Integrated PHY Interface to FPGA, CPLD, ASICs, and so Forth – Direct Interface to One Hard Disk Drive • Enhanced Direct-Memory-Access (EDMA) – Hardware-Assisted Native Command Controller Queuing (NCQ) from up to 32 Entries – Four Transfer Controllers – Supports Port Multiplier and Command- Based Switching – 64/8 Independent DMA/QDMA Channels • Parallel ATA/ATAPI I/F (ATA/ATAPI-6 • Dual Port Ethernet (10/100/1000 Mb/s) With Specification) Optional Switch – PIO, Multiword DMA, and UDMA – IEEE 802.3 Compliant (3.3V I/O Only) • Real-Time Clock (RTC) – MII/RMII/GMII/RGMII Media Independent I/Fs – One-Time or Periodic Interrupt Generation – Management Data I/O (MDIO) Module • Up to 128 General-Purpose I/O (GPIO) Pins – Reset Isolation • One Spin Lock Module with up to 128 Hardware – IEEE-1588 Time-Stamping, AVB, and Semaphores Industrial Ethernet Protocols • One Mailbox Module with 12 Mailboxes • Dual USB 2.0 Ports With Integrated PHYs • On-Chip ARM ROM Bootloader (RBL) – USB2.0 High-/Full-Speed Clients • Power, Reset, and Clock Management – USB2.0 High-/Full-/Low-Speed Hosts, or OTG – Multiple Independent Core Power Domains – Supports End Points 0-15 – Multiple Independent Core Voltage Domains • One PCI Express 2.0 Port With Integrated PHY – Support for Three Operating Points – Single Port With 1 Lane at 5.0 GT/s (OPP166/120/100) per Voltage Domain – Configurable as Root Complex or Endpoint – Clock Enable/Disable Control for • MLB Subsystem (MLBSS) Subsystems and Peripherals – MLB 3-pin or 6-pin interfaces • 32KB Embedded Trace Buffer™ (ETB™) and 5- – Enables Connection to MOST Optical Rings pin Trace Interface for Debug – MOST25/50/150 (up to 100Mbps) • IEEE-1149.1 (JTAG) Compatible • Audio Tracking Logic (ATL) • 684-Pin Pb-Free BGA Package (CYE Suffix), – Asyncronous SRC Assist 0.8-mm Ball Pitch With Via Channel™ • Eight 32-bit General-Purpose Timers (Timer1–8) Technology to Reduce PCB Cost 2 High-Performance System-on-Chip (SoC) Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback |
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