 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
DP83867CRRGZR Datasheet(PDF) 3 Page - Texas Instruments |
|
|
||||||||||||||||||||||||||||||
DP83867CRRGZR Datasheet(HTML) 3 Page - Texas Instruments |
|
|
3 / 132 page  3 DP83867IR, DP83867CR www.ti.com SNLS484D – FEBRUARY 2015 – REVISED JULY 2016 Product Folder Links: DP83867IR DP83867CR Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (November 2015) to Revision D Page • Added Fast Link Drop Configuration Register (FLD_CFG) register ....................................................................................... 3 • Added '(Straps Required)' to RX_DV/RX_CTRL pin in Table 2 ........................................................................................... 10 • Changed '1nF' to '1µF' for VDD1P1 and VDD1P0 pin in Table 2 ........................................................................................ 12 • Added storage temperature to Absolute Maximum Ratings................................................................................................. 13 • Added Operating Junction Temperature to Recommended Operating Conditions .............................................................. 14 • Changed parameter symbol from VIH to VIH in Electrical Characteristics............................................................................ 14 • Added MDC toggling clarification to Reset Timing (2) ............................................................................................................ 17 • Changed target strap voltage thresholds in Table 5 ............................................................................................................ 46 • Changed 'SPEED_SEL1' to 'ANEG_SEL1' in Table 6 ......................................................................................................... 47 • Added '(Straps Required)' to RX_DV/RX_CTRL in Table 6 ................................................................................................. 47 • Changed 'SPEED_SEL0' to 'ANEG_SEL' in Table 6 .......................................................................................................... 48 • Changed 'SPEED_SEL0' to 'ANEG_SEL0' in Table 6 ........................................................................................................ 48 • Changed table name from 'PAP Speed Select Strap Details' to Table 7............................................................................. 49 • Changed 'SPEED_SEL0' and 'SPEED_SEL' to 'ANEG_SEL0' and 'ANEG_SEL1' in Table 7 ............................................ 49 • Changed table name from 'RGZ Speed Select Strap Details' to Table 8 ............................................................................ 49 • Changed 'SPEED_SEL' to 'ANEG_SEL' in Table 8 ............................................................................................................. 49 • Changed Default state of from 'Strap' to '0' for bit 13 in Table 11........................................................................................ 55 • Changed Default state of from 'Strap' to '1' for bit 6 in Table 11.......................................................................................... 56 • Changed bit 9 name from 100BASE-T FULL DUPLEX to 1000BASE-T FULL DUPLEX in Configuration Register 1 (CFG1), Address 0x0009...................................................................................................................................................... 66 • Changed bit 9 descriptions from half duplex to full duplex in Configuration Register 1 (CFG1), Address 0x0009.............. 66 • Changed 'Interrupt Status and Event Control Register (ISR)' to 'MII Interrupt Control Register (MICR)' in MII Interrupt Control Register (MICR) ........................................................................................................................................ 72 • Changed Register definition to move a statement from Interrupt Status Register (ISR) to MII Interrupt Control Register (MICR) ................................................................................................................................................................... 72 • Changed default of bit 9 from '1' to '0' in Configuration Register 2 (CFG2), Address 0x0014 ............................................. 76 • Changed default of bits 5:0 from '0' to '0 0111' in Configuration Register 2 (CFG2), Address 0x0014 ............................... 76 • Added Fast Link Drop Configuration Register (FLD_CFG) register ..................................................................................... 86 • Changed Name of Bits 6:5 from 'STRAP_SPEED_SEL' to 'STRAP_ANEG_SEL' in Table 44 ........................................... 89 • Changed Name of Bit 6 from 'RESERVED' to 'RESERVED (RGZ)' in Table 44 ................................................................. 89 • Changed Name of Bit 5 from 'STRAP_SPEED_SEL (PAP)' to 'STRAP_SPEED_SEL (RGZ)' in Table 44 ........................ 89 • Changed name of Bit 6:4 from 'RESERVED' to 'RESERVED (PAP)' in Table 45 .............................................................. 90 • Added description for 'STRAP_RGMII_CLK_SKEW_TX (RGZ)' in Table 45 ..................................................................... 90 • Changed name of Bit 2:0 from 'RESERVED' to 'RESERVED (PAP)' in Table 45 .............................................................. 90 • Added description for 'STRAP_RGMII_CLK_SKEW_RX (RGZ)' in Table 45 ..................................................................... 90 • Changed default value of bit 4:0 from '10000' to 'TRIM' in I/O Configuration (IO_MUX_CFG) ........................................ 102 • Changed description for IO_IMPEDANCE_CTRL bits in I/O Configuration (IO_MUX_CFG) ............................................ 102 • Changed Power Supply Recommendations section .......................................................................................................... 117 • Added "The 2.5-V VDDA2P5 can come up with or after the 1.8-V VDDA1P8 but not before it" to Power Supply Recommendations ............................................................................................................................................................. 119 • Added Figure 33 ................................................................................................................................................................ 119 • Added Table 124 ............................................................................................................................................................... 119 • Added note regarding 1.8-V supply sequence if no load exists on 2.5-V supply in Layout .............................................. 119 |
Similar Part No. - DP83867CRRGZR |
|
Similar Description - DP83867CRRGZR |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
