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DP83848LFQ Datasheet(PDF) 7 Page - Texas Instruments |
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DP83848LFQ Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 82 page  DP83848LFQ www.ti.com SNLS480A – JULY 2014 – REVISED APRIL 2015 3.3 Serial Management Interface SIGNAL TYPE PIN NO. DESCRIPTION NAME MDC I 25 MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO management data input/output serial interface which may be asynchronous to transmit and receive clocks. The maximum clock rate is 25 MHz with no minimum clock rate. MDIO I/O 24 MANAGEMENT DATA I/O: Bi-directional management instruction/data signal that may be sourced by the station management entity or the PHY. This pin requires a 1.5 k Ω pullup resistor. 3.4 MAC Data Interface SIGNAL TYPE PIN NO. DESCRIPTION NAME TX_CLK O 2 MII TRANSMIT CLOCK: 25 MHz Transmit clock output in 100 Mb/s mode or 2.5 MHz in 10 Mb/s mode derived from the 25 MHz reference clock. Unused in RMII mode. The device uses the X1 reference clock input as the 50 MHz reference for both transmit and receive. TX_EN I, PD 3 MII TRANSMIT ENABLE: Active high input indicates the presence of valid data inputs on TXD[3:0]. RMII TRANSMIT ENABLE: Active high input indicates the presence of valid data on TXD[1:0]. TXD_0 I 4 MII TRANSMIT DATA: Transmit data MII input pins, TXD[3:0], that accept data synchronous to TXD_1 5 the TX_CLK (2.5 MHz in 10 Mb/s mode or 25 MHz in 100 Mb/s mode). TXD_2 6 RMII TRANSMIT DATA: Transmit data RMII input pins, TXD[1:0], that accept data synchronous to TXD_3 I, PD 7 the 50 MHz reference clock. RX_CLK O 31 MII RECEIVE CLOCK: Provides the 25 MHz recovered receive clocks for 100 Mb/s mode and 2.5 MHz for 10 Mb/s mode. Unused in RMII mode. The device uses the X1 reference clock input as the 50 MHz reference for both transmit and receive. RX_DV S, O, PD 32 MII RECEIVE DATA VALID: Asserted high to indicate that valid data is present on the corresponding RXD[3:0]. Mll mode by default with internal pulldown. RMII Synchronous RECEIVE DATA VALID:This signal provide the RMII Receive Data Valid indication independent of Carrier Sense. RX_ER S, O, PU 34 MII RECEIVE ERROR: Asserted high synchronously to RX_CLK to indicate that an invalid symbol has been detected within a received packet in 100 Mb/s mode. RMII RECEIVE ERROR: Asserted high synchronously to X1 whenever an invalid symbol is detected, and CRS_DV is asserted in 100 Mb/s mode. This pin is not required to be used by a MAC in either MII or RMII mode, because the Phy is required to corrupt data on a receive error. RXD_0 S, O, PD 36 MII RECEIVE DATA: Nibble wide receive data signals driven synchronously to the RX_CLK, 25 RXD_1 37 MHz for 100 Mb/s mode, 2.5 MHz for 10 Mb/s mode). RXD[3:0] signals contain valid data when RXD_2 38 RX_DV is asserted. RXD_3 39 RMII RECEIVE DATA: 2-bits receive data signals, RXD[1:0], driven synchronously to the X1 clock, 50 MHz. CRS/CRS_DV S, O, PU 33 MII CARRIER SENSE: Asserted high to indicate the receive medium is non-idle. RMII CARRIER SENSE/RECEIVE DATA VALID: This signal combines the RMII Carrier and Receive Data Valid indications. For a detailed description of this signal, see the RMII Specification. COL S, O, PU 35 MII COLLISION DETECT: Asserted high to indicate detection of a collision condition (simultaneous transmit and receive activity) in 10 Mb/s and 100 Mb/s Half Duplex Modes. While in 10BASE-T Half Duplex mode with heartbeat enabled this pin is also asserted for a duration of approximately 1µs at the end of transmission to indicate heartbeat (SQE test). In Full Duplex Mode, for 10 Mb/s or 100 Mb/s operation, this signal is always logic 0. There is no heartbeat function during 10 Mb/s full duplex operation. RMII COLLISION DETECT: Per the RMII Specification, no COL signal is required. The MAC will recover CRS from the CRS_DV signal and use that along with its TX_EN signal to determine collision. Copyright © 2014–2015, Texas Instruments Incorporated Pin Configuration and Functions 7 Submit Documentation Feedback |
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