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DP8573A Datasheet(PDF) 8 Page - Texas Instruments |
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DP8573A Datasheet(HTML) 8 Page - Texas Instruments |
8 / 18 page Functional Description (Continued) XTAL Co Ct ROUT 32768 kHz 47 pF 2 pF – 22 pF 150 kX to 350 kX INTERRUPT LOGIC FUNCTIONAL DESCRIPTION The RTC has the ability to coordinate processor timing ac- tivities To enhance this an interrupt structure has been im- plemented which enables several types of events to cause interrupts Interrupts are controlled via two Control Regis- ters in block 1 and two Status Registers in block 0 (See Register Description for notes on paging and Table I) The interrupts are enabled by writing a one to the appropri- ate bits in Interrupt Control Register 0 andor 1 TABLE I Registers that are Applicable to Interrupt Control Register Name Register Address Select Main Status Register X 00H Periodic Flag Register 0 03H Interrupt Control Register 0 1 03H Interrupt Control Register 1 1 04H Output Mode Register 1 02H The Interrupt Status Flag D0 in the Main Status Register indicates the state of INTR and MFO outputs It is set when either output becomes active and is cleared when all RTC interrupts have been cleared and no further interrupts are pending (ie both INTR and MFO are returned to their inac- tive state) This flag enables the RTC to be rapidly polled by the mP to determine the source of an interrupt in a wired OR interrupt system (The Interrupt Status Flag provides a true reflection of all conditions routed to the external pins) Status for the interrupts are provided by the Main Status Register and the Periodic Flag Register Bits D1 – D5 of the Main Status Register are the main interrupt bits These register bits will be set when their associated timing events occur Enabled Alarm comparisons that occur will set its Main Status Register bit to a one However an exter- nal interrupt will only be generated if the Alarm interrupt enable bit is set (see Figure 5 ) Disabling the periodic interrupts will mask the Main Status Register periodic bit but not the Periodic Flag Register bits The Power Fail Interrupt bit is set when the interrupt is en- abled and a power fail event has occurred and is not reset until the power is restored If all interrupt enable bits are 0 no interrupt will be asserted However status still can be read from the Main Status Register in a polled fashion (see Figure 5 ) To clear a flag in bits D2 and D3 of the Main Status Register a 1 must be written back into the bit location that is to be cleared For the Periodic Flag Register reading the status will reset all the periodic flags Interrupts Fall Into Three Categories 1 The Alarm Compare Interrupt Issued when the value in the time compared RAM equals the counter 2 The Periodic Interrupts These are issued at every incre- ment of the specific clock counter signal Thus an inter- rupt is issued every minute second etc Each of these interrupts occurs at the roll-over of the specific counter 3 The Power Fail Interrupt Issued upon recognition of a power fail condition by the internal sensing logic The power failed condition is determined by the signal on the PFAIL pin The internal power fail signal is gated with the chip select signal to ensure that the power fail interrupt does not lock the chip out during a read or write ALARM COMPARE INTERRUPT DESCRIPTON The alarmtime comparison interrupt is a special interrupt similar to an alarm clock wake up buzzer This interrupt is generated when the clock time is equal to a value pro- grammed into the alarm compare registers Up to six bytes can be enabled to perform alarm time comparisons on the counter chain These six bytes or some subset thereof would be loaded with the future time at which the interrupt will occur Next the appropriate bits in the Interrupt Control Register 1 are enabled or disabled (refer to detailed descrip- tion of Interrupt Control Register 1) The RTC then com- pares these bytes with the clock time When all the enabled compare registers equal the clock time an alarm interrupt is issued but only if the alarm compare interrupt is enabled can the interrupt be generated externally Each alarm com- pare bit in the Control Register will enable a specific byte for comparison to the clock Disabling a compare byte is the same as setting its associated counter comparator to an ‘‘always equal’’ state For example to generate an interrupt at 315 AM of every day load the hours compare with 0 3 (BCD) the minutes compare with 1 5 (BCD) and the faster counters with 0 0 (BCD) and then disable all other compare registers So every day when the time rolls over from 3145999 an interrupt is issued This bit may be reset by writing a one to bit D3 in the Main Status Register at any time after the alarm has been generated If time comparison for an individual byte counter is disabled that corresponding RAM location can then be used as gen- eral purpose storage PERIODIC INTERRUPTS DESCRIPTION The Periodic Flag Register contains six flags which are set by real-time generated ‘‘ticks’’ at various time intervals see Figure 5 These flags constantly sense the periodic signals and may be used whether or not interrupts are enabled These flags are cleared by any read or write operation per- formed on this register To generate periodic interrupts at the desired rate the asso- ciated Periodic Interrupt Enable bit in Interrupt Control Reg- ister 0 must be set Any combination of periodic interrupts may be enabled to operate simultaneously Enabled period- ic interrupts will now affect the Periodic Interrupt Flag in the Main Status Register When a periodic event occurs the Periodic Interrupt Flag in the Main Status Register is set causing an interrupt to be generated The mP clears both flag and interrupt by writing a ‘‘1’’ to the Periodic Interrupt Flag The individual flags in the periodic Interrupt Flag Register do not require clearing to cancel the interrupt If all periodic interrupts are disabled and a periodic interrupt is left pending (ie the Periodic Interrupt Flag is still set) the Periodic Interrupt Flag will still be required to be cleared to cancel the pending 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