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DRV3201-Q1 Datasheet(PDF) 6 Page - Texas Instruments |
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DRV3201-Q1 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 60 page  DRV3201-Q1 SLVSBD6D – MAY 2012 – REVISED AUGUST 2015 www.ti.com Pin Functions (continued) PIN TYPE(1) DESCRIPTION NO. NAME VCC3 regulator, for internal use only. Recommended external decoupling capacitance: 4.7 nF. 42 VCC3 LVO_A External load < 100 µA AMUX Analog TEST output MUX, connected to GND during normal application. 43 LVO_A (GND) 44 ADREF LVI_A ADC reference of MCU, used as maximum voltage clamp for O1-O4. 45 GNDL GND Logic ground 46 O4 LVO_A Output second stage current sense amplifier 2 47 O3 LVO_A Output second stage current sense amplifier 1 48 O2 LVO_AO Output first stage current sense amplifier 2 49 IN2 HVI_A Current sense input N 2 50 IP2 HVI_A Current sense input P 2 51 GNDA GND Ground analog 52 RO LVO_A Current sense reference output for the shift voltage. 53 RI HVI_A Current sense reference input for the shift voltage. 54 IP1 HVI_A Current sense input P 1 55 O1 LVO_A Output first stage current sense amplifier 1 56 IN1 HVI_A Current sense input N 1 57 GNDA GND Ground analog 58 VDDIO Supply IO supply voltage, defines the interface voltage of digital I/O, for example, SPI. 59 IHS3 HVI_D Input HS 3, digit input to drive the HS3 60 ILS3 HVI_D Input LS 3, digit input to drive the LS3 61 IHS2 HVI_D Input HS 2, digit input to drive the HS2 62 ILS2 HVI_D Input LS 2, digit input to drive the LS2 63 IHS1 HVI_D Input HS 1, digit input to drive the HS1 64 ILS1 HVI_D Input LS 1, digit input to drive the LS1 6 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DRV3201-Q1 |
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