AD7908/AD7918/AD7928

REV. A

Parameter

Unit

Description

2

10

10

kHz min

20

20

MHz max

16

16

50

50

ns min

Minimum Quiet Time Required between

CS Rising Edge

and Start of Next Conversion

10

10

ns min

CS to SCLK Setup Time

3

35

30

ns max

Delay from

CS until DOUT Three-State Disabled

3

40

40

ns max

Data Access Time after SCLK Falling Edge

0.4

0.4

ns min

SCLK Low Pulse Width

0.4

0.4

ns min

SCLK High Pulse Width

10

10

ns min

SCLK to DOUT Valid Hold Time

4

15/45

15/35

ns min/max

SCLK Falling Edge to DOUT High Impedance

10

10

ns min

DIN Setup Time Prior to SCLK Falling Edge

55

ns min

DIN Hold Time after SCLK Falling Edge

20

20

ns min

Sixteenth SCLK Falling Edge to

CS High

11

µs max

Power-Up Time from Full Power-Down/Auto Shutdown Mode

NOTES

See Figure 1. The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.

time of the part and is independent of the bus loading.

Specifications subject to change without notice.

TO

OUTPUT

PIN

50pF

200 A

200 A

1.6V

Figure 1. Load Circuit for Digital Output Timing Specifications

–8–