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DS125DF111SQE Datasheet(PDF) 4 Page - Texas Instruments |
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DS125DF111SQE Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 54 page  DS125DF111 SNLS450A – JANUARY 2014 – REVISED JUNE 2015 www.ti.com Pin Functions (continued) PIN I/O TYPE DESCRIPTION NAME NO. INDICATOR PINS LOCK 16 O, LVCMOS LOCK VOH is referenced to VIN voltage level. Note that this pin is shared with strap input functions read at startup. The Address value loaded into pin 16 (ADDR0) at startup changes the definition of the LOCK pin output. See the Shared Register Definition in Table 7 for more details. LOS/INT# 13 O, Open Drain Output is driven LOW when a valid signal is present on INA. Output is released when signal on INA is lost (LOS). This output can be redefined as an INT# signal which will be driven LOW for any of the following conditions.(1) 1. The EOM check returns a value below the HEO/VEO interrupt threshold. 2. CDR check returns lock/loss status. 3. Signal Detector returns detect/loss status. SMBus MODE PINS ENSMB 3 I, 4-Level System Management Bus (SMBus) enable pin HIGH = Register Access, SMBus Slave mode FLOAT = SMBus Master read from External EEPROM 20 K to GND = Reserved LOW = External Pin Control Mode. See section on Pin Mode Limitation SDA 4 I, SMBus Data Input / Open Drain Output O, Open Drain External pull-up resistor is required. Pin is 3.3 V LVCMOS tolerant(1) SCL 5 I, SMBus Clock input in SMBus slave mode. Can also be an open drain output in O, Open Drain SMBus master mode Pin is 3.3 V LVCMOS Tolerant (1) TX_DIS 6 I, 4-Level Disable the OUTB transmitter HIGH = OUTA Enabled/OUTB Disabled FLOAT = Reserved 20 K to GND = Reserved LOW = OUTA/OUTB Enabled (normal operation) ADDR0 16 I, LVCMOS This pin sets the SMBus address for the retimer. This pin is a strap input. The state is read on power-up to set the SMBus address in SMBus control mode. The latched value of ADDR0 read at startup will change the LOCK output definition. See the Shared Register Definition in Table 7 for more details.(2) ADDR1/DONE# 10 IO, LVCMOS This pin sets the SMBus address for the retimer in SMBus Slave Mode. DONE#. VOH is referenced to VIN voltage level. DONE# goes low to indicate that the SMBus master EEPROM read has been completed in SMBus Master Mode(2) READEN# 9 I, LVCMOS Initiates SMBus master EEPROM read. When multiple DS125DF111 are connected to a single EEPROM, the READEN# input can be daisy chained to the DONE# output. In SMBus Slave Mode this pin should be tied to Logic 0. (3) PIN CONTROL (ENSMB = LOW) (4) DEMA 4 I, 4-Level Set CHA output de-emphasis level in pin control mode (3) DEMB 5 I, 4-Level Set CHB output de-emphasis level in pin control mode (3) LPBK 6 I, 4-Level HIGH = INA goes to OUTA, INB goes to OUTB FLOAT = INB goes to OUTA and OUTB 20 K to GND = INA goes to OUTA and OUTB LOW = INA goes to OUTB, INB goes to OUTA (3) VODA 9 I, 4-Level Set CHA output launch amplitude in pin control mode (3). VODB 10 I, 4-Level Set CHB output launch amplitude in pin control mode(3) (1) The LOS/INT# pin is an open drain output which requires external pull-up resistor (typically connected to 2.5 V or 3.3 V for system logic compatibility) to achieve a HIGH level. (2) This pin is shared with other functions. (3) This pin is shared with other functions. (4) When in pin control mode, the DS125DF111 device operates at 12.288, 9.8304, 6.144, 4.9152, 3.072, 2.4576, 1.536, or 1.2288 Gbps and has limited VOD and De-Emphasis control. See Table 9. 4 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: DS125DF111 |
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