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CDCVF855PWRG4 Datasheet(PDF) 5 Page - Texas Instruments |
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CDCVF855PWRG4 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 16 page www.ti.com TIMING REQUIREMENTS CDCVF855 SCAS839A – APRIL 2007 – REVISED MAY 2007 ELECTRICAL CHARACTERISTICS (continued) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT fO = 170 MHz 65 80 Without load fO = 200 MHz 75 90 fO = 170 MHz 110 140 Differential outputs terminated IDD Dynamic current on VDDQ mA with 120 Ω, C L = 0 pF fO = 200 MHz 120 150 fO = 170 MHz 130 160 Differential outputs terminated with 120 Ω, C L = 14 pF fO = 200 MHz 140 170 Part-to-part input capacitance ∆C VDDQ = 2.5 V, VI = VDDQ or GND 1 pF variation Input capacitance difference CI(∆) between CLK and CLK, FBIN VDDQ = 2.5 V, VI = VDDQ or GND 0.25 pF and FBIN over recommended ranges of supply voltage and operating free-air temperature PARAMETER MIN MAX UNIT Operating clock frequency 60 220 fCLK MHz Application clock frequency 90 220 Input clock duty cycle 40% 60% Stabilization time (PLL mode)(1) 10 µs Stabilization time (bypass mode)(2) 30 ns (1) The time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK and VDD must be applied. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under SSC application. (2) A recovery time is required when the device goes from power-down mode into bypass mode (AVDD at GND). 5 Submit Documentation Feedback |
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