CDCVF310_15 datasheet(7/16 Pages) TI1

Part #	CDCVF310

Description	2.5-V TO 3.3-V HIGH-PERFORMANCE CLOCK BUFFER

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Manufacturer	TI1 [Texas Instruments]

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JITTER CHARACTERISTICS

SWITCHING CHARACTERISTICS

CDCVF310

SCAS771B – AUGUST 2004 – REVISED JANUARY 2008

Characterized using CDCVF310 Performance EVM when VDD=3.3 V. Outputs not under test are terminated to 50 Ω.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

12 kHz to 5 MHz, fout = 30.72 MHz

47

tjitter

Additive phase jitter from input to output 1Y0

fs rms

12 kHz to 20 MHz, fout = 125 MHz

40

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP(1)

MAX

UNIT

VDD = 3.3 V ±0.3 V (see Figure 2)

tPLH

1

2.8

CLK to Yn

f = 0 MHz to 200 MHz

ns

tPHL

1

2.8

tsk(o)

Output skew (Ym to Yn) (2) (see Figure 4)

100

150

ps

tsk(p)

Pulse skew (see Figure 5)

250

ps

tsk(pp)

Part-to-part skew

350

ps

tr

Rise time

VO = 0.4 V to 2 V

1.3

2.7

V/ns

tf

Fall time

VO = 2 V to 0.4 V

1.3

2.7

V/ns

tsu(en)

Enable setup time, G_high before CLK

↓

0.1

ns

tsu(dis)

Disable setup time, G_low before CLK

↓

0.1

ns

th(en)

Enable hold time, G_high after CLK

↓

0.4

ns

th(dis)

Disable hold time, G_low after CLK

↓

0.4

ns

VDD = 2.5 V ±0.2 V (see Figure 2)

tPLH

1.3

4

CLK to Yn

f = 0 MHz to 200 MHz

ns

tPHL

1.3

4

tsk(o)

Output skew (Ym to Yn) (2) (see Figure 4 )

150

230

ps

tsk(p)

Pulse skew (see Figure 5)

280

ps

tsk(pp)

Part-to-part skew

400

ps

tr

Rise time

VO = 0.4 V to 1.7 V

0.5

1.6

V/ns

tf

Fall time

VO = 1.7 V to 0.4 V

0.5

1.6

V/ns

tsu(en)

Enable setup time, G_high before CLK

↓

0.1

ns

tsu(dis)

Disable setup time, G_low before CLK

↓

0.1

ns

th(en)

Enable hold time, G_high after CLK

↓

0.4

ns

th(dis)

Disable hold time, G_low after CLK

↓

0.4

ns

(1)

All typical values are with respect to nominal VDD.

(2)

The tsk(o) specification is only valid for equal loading of all outputs.

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