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DP83891 Datasheet(PDF) 1 Page - National Semiconductor (TI) |
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DP83891 Datasheet(HTML) 1 Page - National Semiconductor (TI) |
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1 / 2 page  © 2000 National Semiconductor Corporation www.national.com Subject to change Last Modified: 1/27/00 REVISION 0.0 Advance Information January 2000 DP83891 Gig PHYTER ™ 10/100/1000M General Description The DP83891 is the first fully integrated, feature rich Physi- cal Layer transceiver with integrated PMD sublayers to sup- port 10BASE-T,100BASE-TX and 1000BASE-T Ethernet protocols. It operates on existing CAT5 cables which reduces deployment costs. The DP83891 is designed for easy implementation of 10/100/1000 Mb/s Ethernet LANs. It interfaces directly to Twisted Pair media via an external standard Quad trans- former. The DP83891 connects to the MAC layer through the IEEE 802.3u Standard Media Independent Interface (MII) or the IEEE 802.3z Gigabit Media Independent Inter- face (GMII). Applications The DP83891 fits applications in: s 10/100/1000 Mb/s capable node cards s Switches with 10/100/1000 Mb/s capable ports s High speed uplink ports (backbone) s High end workstations System Diagram TRI-STATE® is a registered trademark of National Semiconductor Corporation. ETHERNET DP83891 ETHERNET PHYSICAL LAYER STATUS LED RJ-45 100BASE-TX MII/GMII MAC 100BASE-TX CLOCK 125 MH 1000BASE-T or 1000BASE-T z s or 10/100/1000 10/100/1000 Mb/s 10BASE-T, 10BASE-T, Features s Fully integrated 10BASE-T,100BASE-TX and 1000BASE-T capable s Single Quad TX-Transformer interface for all speeds s Fully compliant to IEEE 802.3u 100BASE-TX and IEEE 802.3z/ab 1000BASE-T specifications. Fully integrated and fully compliant ANSI X3.T12 PMD physical sublayer that includes adaptive equalization and Baseline Wan- der compensation. s Supports Auto-MDIX s IEEE 802.3u Auto-Negotiation and Parallel Detection – Fully auto-negotiates between 10, 100 and 1000 Mb/s full duplex and half duplex devices s 3.3 V MAC interfaces: – IEEE 802.3u MII – IEEE 802.3z GMII s LED support (Link, Speed, Activity, Duplex, Collision, Auto-Negotiation, TX and RX indications) s Management Register Set (MDIO and MDC) s Single 3.3 V power supply – 5 V tolerant I/Os s 208-pin PQFP package |
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