CDCR61A

DIRECT RAMBUS

™ CLOCK GENERATOR – LITE

SCAS626 – FEBRUARY 2000

6

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

39

Ω, ±5%

68

Ω, ±5%

68

Ω, ±5%

3 pF

See Note A

100 pF

39

Ω, ±5%

3 pF

See Note A

RT = 28 Ω

RT = 28 Ω

(CLK)

Measurement

Node

(CLKB)

NOTE A: These capacitors represent parasitic capacitance. No discrete capacitors are used on the test

board during device characterization.

CLK

CLKB

tc1

tc2

Cycle-to-cycle jitter = | tc1 – tc2| over 10000 consecutive cycles

Figure 2. Cycle-to-Cycle Jitter

CLK

CLKB

tc(i)

tc(i) = nominal expected time

Cycle-to-cycle jitter = | tc(i) – tc(i+1)| over 10000 consecutive cycles

tc(i+1)

Figure 3. Short-Term Cycle-to-Cycle Jitter over 2, 3, 4, or 6 Cycles

CLK

CLKB

t(cycle)

tjL = | t(cycle), max– t(cycle), min| over 10000 consecutive cycles

Figure 4. Long-Term Jitter